S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 186

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 32
5.2.1 Registers
S1D13505
X23A-G-003-07
REG[10h] Screen 1 Display Start Address 0
REG[11h] Screen 1 Display Start Address 1
REG[12h] Screen 1 Display Start Address 2
Start Addr
Start Addr
Bit 15
Bit 7
n/a
Start Addr
Start Addr
Bit 14
Bit 6
n/a
Both panning and scrolling are performed by modifying the start address register. The start
address refers to the word offset in the display buffer where the image will start being
displayed from. At color depths less than 15 bpp a second register, the pixel pan register, is
required for smooth pixel level panning.
Internally, the S1D13505 latches different signals at different times. Due to this internal
sequence, there is an order in which the start address and pixel pan registers should be
accessed during scrolling operations to provide the smoothest scrolling. Setting the
registers in the wrong sequence or at the wrong time will result in a “tearing” or jitter effect
on the display.
The start address is latched at the beginning of each frame, therefore the start address can
be set any time during the display period. The pixel pan register values are latched at the
beginning of each display line and must be set during the vertical non-display period. The
correct sequence for programing these registers is:
1. Wait until just after a vertical non-display period (read register [0Ah] and watch bit 7
2. Update the start address registers.
3. Wait until the next vertical non-display period.
4. Update the pixel paning register.
These three registers form the address of the word in the display buffer where screen 1 will
start displaying from. Changing these registers by one will cause a change of 0 to 16 pixels
depending on the current color depth. Refer to the following table to see the minimum
number of pixels affected by a change of one to these registers.
for the non-display status).
Start Addr
Start Addr
Figure 5-3: Screen 1 Start Address Registers
Bit 13
Bit 5
n/a
Start Addr
Start Addr
Bit 12
Bit 4
n/a
Start Addr
Start Addr
Start Addr
Bit 11
Bit 19
Bit 3
Start Addr
Start Addr
Start Addr
Bit 10
Bit 18
Bit 2
Epson Research and Development
Start Addr
Start Addr
Start Addr
Programming Notes and Examples
Bit 17
Bit 1
Bit 9
Vancouver Design Center
Issue Date: 01/02/05
Start Addr
Start Addr
Start Addr
Bit 16
Bit 0
Bit 8