IDT82P2282 Integrated Device Technology, Inc., IDT82P2282 Datasheet - Page 157

• Manufacturer Part Number: IDT82P2282
• Description: 2 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2282
T1/J1 RBIF Option Register (046H, 146H)
FBITGAP:
DE:
and MRSIG.
FE:
CMS:
010H) is set to ‘1’), the bit of the two links should be set to the same value.
TRI:
Programming Information
Bit Name
Default
Bit No.
Type
This bit is valid in Receive Clock Master mode.
= 0: The F-bit is not gapped.
= 1: The F-bit is gapped (no clock signal during the F-bit).
This bit selects the active edge of RSCKn to update the data on RSDn and RSIGn and the active edge of MRSCK to update the data on MRSD
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Receive Multiplexed mode, the bit of the two links should be set to the same value.
This bit selects the active edge of RSCKn to update/sample the pulse on RSFSn and the active edge of MRSCK to sample the pulse on MRSFS.
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Receive Multiplexed mode, the bit of the two links should be set to the same value.
This bit is valid in Receive Clock Slave T1/J1 mode E1 rate and Receive Multiplexed mode.
= 0: The speed of the RSCKn/MRSCK is the same as the data rate on the system side (2.048 MHz / 8.192 MHz).
= 1: The speed of the RSCKn/MRSCK is double the data rate on the system side (4.096 MHz / 16.384 MHz).
In Receive Clock Slave T1/J1 mode E1 rate, if both two links use the RSCK[1] and RSFS[1] to output the data (i.e., the RSLVCK bit (b, T1/J1-
In Receive Multiplexed mode, the bit of the two links should be set to the same value.
= 0: The processed data and signaling bits are output on the RSDn/MRSD pins and the RSIGn/MRSIG pins respectively.
= 1: The output on the RSDn/MRSD pins and the RSIGn/MRSIG pins are in high impedance.
7
Reserved
6
5
FBITGAP
R/W
4
0
146
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
R/W
DE
3
1
R/W
FE
2
1
CMS
R/W
1
0
October 7, 2003
R/W
TRI
0
1