IDT82P2282 Integrated Device Technology, Inc., IDT82P2282 Datasheet - Page 58
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IDT82P2282
Manufacturer Part Number
IDT82P2282
Description
2 Channel T1/J1/E1 Transceiver
Manufacturer
Integrated Device Technology, Inc.
Datasheet
1.IDT82P2282.pdf
(383 pages)
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IDT82P2282
means there is an interrupt. The interrupt will be reported by the INT pin
if its Interrupt Enable bit is ‘1’.
Functional Description
Table 31: Related Bit / Register In Chapter 3.11.2
ADRM[1:0]
RHDLCM
LSSUFIL
DAT[7:0]
FISUFIL
RMBEE
HA[7:0]
OVFLE
LA[7:0]
RMBEI
OVFLI
RRST
PACK
EMP
Bit
RHDLC1 Interrupt Control / RHDLC2 Interrupt Control / RHDLC3 Interrupt
RHDLC1 High Address / RHDLC2 High Address / RHDLC3 High Address
RHDLC1 Control Register / RHDLC2 Control Register / RHDLC3 Control
RHDLC1 Low Address / RHDLC2 Low Address / RHDLC3 Low Address
RHDLC1 Interrupt Indication / RHDLC2 Interrupt Indication / RHDLC3
RHDLC1 Data / RHDLC2 Data / RHDLC3 Data
RHDLC1 RFIFO Access Status /
Interrupt Indication
Register
Register
Control
47
to ‘1’ on the RRST bit. The reset will clear the FIFO, the PACK bit and
the EMP bit.
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
The HDLC Receiver will be reset when there is a transition from ‘0’
09B, 19B / 09C, 19C / 09D, 19D
0A1, 1A1 / 0A2, 1A2 / 0A3, 1A3
0A4, 1A4 / 0A5, 1A5 / 0A6, 1A6
09E, 19E / 09F, 19F / 0A0, 1A0
098, 198 / 099, 199 / 09A, 19A
092, 192 / 093, 193 / 094, 194
095, 195 / 096, 196 / 097, 197
Address (Hex)
October 7, 2003
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