ADP5034-1-EVALZ Analog Devices, ADP5034-1-EVALZ Datasheet - Page 20
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ADP5034-1-EVALZ
Manufacturer Part Number
ADP5034-1-EVALZ
Description
Manufacturer
Analog Devices
Datasheet
1.ADP5034-1-EVALZ.pdf
(28 pages)
ADP5034
the input conditions change again and the required duty cycle
falls, the buck immediately restarts PWM regulation without
allowing overshoot on the output voltage.
Active Pull-Downs
All regulators have optional, factory programmable, active pull-
down resistors discharging the respective output capacitors
when the regulators are disabled. The pull-down resistors are
connected between VOUTx and AGND. Active pull-downs are
disabled when the regulators are turned on. The typical value of
the pull-down resistor is 600 Ω for the LDOs and 75 Ω for the
bucks. Figure 46 shows the activation timings for the active
pull-downs during regulator activation and deactivation.
LDO1 AND LDO2
The ADP5034 contains two LDOs with low quiescent current
and low dropout linear regulators, and provides up to 300 mA
of output current. Drawing a low 10 μA quiescent current
(typical) at no load makes the LDO ideal for battery-operated
portable equipment.
Each LDO operates with an input voltage of 1.7 V to 5.5 V. The
wide operating range makes these LDOs suitable for cascading
configurations where the LDO supply voltage is provided from
one of the buck regulators.
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Each LDO output voltage is set through external resistor
dividers as shown in Figure 48 for LDO1. The output voltage
can optionally be factory programmed to default values as
indicated in the Ordering Guide section. In this event, Ra and
Rb are not needed, and FB3 can be left unconnected. FB3 is 0.5 V.
The LDOs also provide high power supply rejection ratio
(PSRR), low output noise, and excellent line and load transient
response with only a small 1 μF ceramic input and output
capacitor.
LDO1 is optimized to supply analog circuits because it offers
better noise performance compared to LDO2. LDO1 should be
used in applications where noise performance is critical.
VIN3
V
OUT3
Figure 48. LDO1 External Output Voltage Setting
= V
FB3
LDO1
Rb
Ra
+ 1
VOUT3
FB3
Ra
Rb
C7
1µF
VOUT3