ADXRS453 Analog Devices, ADXRS453 Datasheet - Page 18

• Manufacturer Part Number: ADXRS453
• Description: High Performance / Digital Output Gyroscope
• Manufacturer: Analog Devices

www.DataSheet4U.com
ADXRS453
FAULT REGISTER BIT DEFINITIONS
Table 14 describes the bits available for signaling faults to
the user. The individual bits of the fault registers are updated
asynchronously, depending on their respective detection criteria;
however, it is recommended that the fault registers be read at a
rate of at least 250 Hz. When asserted, an individual status bit
is not deasserted until it is read by the master device. If the error
persists after a fault register read, the status bit is immediately
reasserted and remains asserted until the next sequential command/
response exchange. The bits in the FAULT0 register are appended
to every sensor data response (see Table 10). Both fault registers
can be accessed by issuing a read command to Address 0x0A.
Table 14. Fault Register Bit Definitions
Register
FAULT1
FAULT0
Fail Bit
The fail flag is asserted when the ST[1:0] bits are set to 00 (see
the ST1 and ST0 Bits section). Assertion of the fail bit indicates
that the device has experienced a gross failure and that the sensor
data could be invalid.
AMP Bit
The AMP fault bit is asserted when the measured amplitude
of the silicon resonator has been significantly reduced. This
condition can occur if the voltage supplied to CP5 falls below
the requirements of the internal voltage regulator. This fault bit
is OR’ e d with the CST fault bit; therefore, during a sensor data
request, the CST bit position represents either an AMP failure
or a CST failure. The full fault register can be read from memory
to determine the specific failure.
OV Bit
The OV fault bit is asserted if the internally regulated voltage
(nominally 3 V) is observed to exceed 3.3 V. This measurement
is low-pass filtered to prevent artifacts such as noise spikes from
asserting a fault condition. When an OV fault occurs, the PWR
fault bit is asserted simultaneously. Because the OV fault bit is not
transmitted as part of a sensor data response, it is recommended
that the user read back the FAULT1 and FAULT0 memory
registers upon the assertion of a PWR error to determine the
specific error condition.
Bit Name
Fail
AMP
OV
UV
PLL
Q
NVM
POR
PWR
CST
CHK
Description
Failure that sets the ST[1:0] bits to 00
Amplitude detection failure
Regulator overvoltage
Regulator undervoltage
Phase-locked loop failure
Quadrature error
Nonvolatile memory fault
Power-on or reset failed to initialize
Power regulation failed due to over-
voltage or undervoltage condition
Continuous self-test failure or amplitude
detection failed
Check: generate faults
Rev. 0 | Page 18 of 32
UV Bit
The UV fault bit is asserted if the internally regulated voltage
(nominally 3 V) is observed to be less than 2.77 V. This mea-
surement is low-pass filtered to prevent artifacts such as noise
spikes from asserting a fault condition. When a UV fault occurs,
the PWR fault bit is asserted simultaneously. Because the UV
fault bit is not transmitted as part of a sensor data response, it is
recommended that the user read back the FAULT1 and FAULT0
memory registers upon the assertion of a PWR error to determine
the specific error condition.
PLL Bit
The PLL bit indicates that the device has experienced a failure
in the phase-locked loop functional circuit block. This occurs
when the PLL fails to achieve synchronization with the resonator
structure. If the PLL status flag is active, the ST[1:0] bits of the
sensor data response are set to 00, indicating that the response
contains potentially invalid rate data.
Q Bit
A Q fault is asserted based on two independent quadrature
calculations.
•
•
NVM Bit
An NVM error is transmitted to the control module when the
internal nonvolatile memory data fails a checksum calculation.
This check is performed once every 50 μs and does not include
the PIDx memory registers.
POR Bit
An internal check is performed on device startup to ensure that
the volatile memory of the device is functional. This is accom-
plished by programming a known value from the device ROM
into a volatile memory register. This value is then continuously
compared to the known value in ROM every 1 μs for the duration
of the device operation. If the value stored in the volatile memory
changes or does not match the value stored in ROM, the POR
error flag is asserted. The value stored in ROM is rewritten to
the volatile memory upon a device power cycle.
The quad memory register (Address 0x08) contains a value
corresponding to the total instantaneous quadrature present
in the device. If this value exceeds 4096 LSB, a Q fault is
issued.
An internal quadrature accumulator records the amount
of quadrature correction performed by the ADXRS453. A
Q fault is issued when the quadrature error present in the
device has contributed to an equivalent of 4°/sec (typical)
of rate offset.