XR17D158 Exar Corporation, XR17D158 Datasheet - Page 38

• Manufacturer Part Number: XR17D158
• Description: Eight-channel Pci-bus Uart
• Manufacturer: Exar Corporation

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PRELIMINARY
Baud Rate Generator Divisors (DLL and DLM)
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter and
receiver. The rate is programmed through registers DLL and DLM which are only accessible when LCR bit-7 is
set to logic 1. See Programmable Baud Rate Generator section for more detail.
INTERRUPT ENABLE REGISTER (IER)
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) register and
also encoded in INT (INT0-INT3) register in the Device Configuration Registers.
IER
When the receive FIFO (FCR BIT-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the
RHR interrupts (see ISR bits 3 and 4) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
IER
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the D158 in the FIFO polled
mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used
in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT 1-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
C. LSR BIT-5 indicates THR is empty.
D. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
E. LSR BIT-7 indicates the Or’ed function of errors in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt. (default)
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This interrupt is associated with bit-5 in the LSR register. An interrupt is issued whenever the THR becomes
empty or when data in the FIFO falls below the programmed trigger level.
Logic 0 = Disable Transmit Holding Register empty interrupt. (default)
Logic 1 = Enable Transmit Holding Register empty interrupt.
IER[2]: Receive Line Status Interrupt Enable
Any of the LSR register bits 1,2,3 or 4 becomes active will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO.
Logic 0 = Disable the receiver line status interrupt. (default)
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt. (default)
Logic 1 = Enable the modem status register interrupt.
IER[4]:
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
VERSUS
VERSUS
Reserved.
R
R
ECEIVE
ECEIVE
/T
FIFO I
RANSMIT
NTERRUPT
FIFO P
M
OLLED
ODE
O
M
PERATION
ODE
O
PERATION
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UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
XR17D158
REV. P1.0.0