HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 21

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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3.2.2.2 Logical device control registers
3.2.3 ISA Plug and Play configuration registers
3.2.3.1 I/O port configuration registers
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register address
control register
Plug and Play
Plug and Play
configuration
address
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30h
31h
60h
61h
Only bits[11:0] are checked by the HFC-SP's internal address decoder in PnP mode.
Write
Write
Read
Read
r/w
r/w
r/w
r/w
Accessable in state
Accessable in state
Config state
Config state
Config state
Config state
Activate register. Setting bit 0 to a one activates the
card on the ISA bus. When cleared, the card cannot
respond to any ISA bus transactions (other than
accesses to its Plug and Play configuration ports).
Reset clears bit 0. Bits[7:1] are reserved and return
zeros when read.
The HFC-SP only supports one logical device, so it is
not necessary to write the logical device number into
the card's logical device number register prior to
writing to this register.
I/O range check register.
Bit(s) Description
7:2
1
0
I/O decoder 0 base address upper byte.
I/O port base address bits[15:8].
I/O decoder 0 base address lower byte.
I/O port base address bits[7:0].
Reserved, return zero when read
When set to one, enables I/O range checking
and disables it when cleared to zero. When
enabled, bit 0 is used to select a pattern for the
logical device to return.
This bit is only valid if the logical device is
deactivated (see Activate register).
When set, the logical device returns 55h in
response to any read from the logical device's
assigned I/O space. When cleared, AAh is
returned.
Description
Description
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Cologne
Chip
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