HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 45

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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Name
SCTRL
SCTRL_E
Addr.
31h
32h
Bits
6..5
0
1
2
3
4
5
6
7
0
1
2
3
4
7
r/w Function
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
'1' B1 data enabled
'0' B2 send data disabled (permanent 1 sent in activated states,
'1' B2 data enabled
S/T interface mode
'0' TE mode (reset default)
'1' NT mode
D-channel priority
'0' high priority 8/9 (reset default)
'1' low priority 10/11
S/Q bit transmission
'0' S/Q bit disable (reset default)
'1' S/Q bit and multiframe enable
'0' normal operation (reset default)
'1' send 96kHz transmit test signal (alternating zeros)
TX_LO line setup
This bit must be configured depending on the used S/T module
and circuitry to match the 400 pulse mask test.
'0' capacitive line mode (reset default)
'1' non capacitive line mode
Power down
'0' power up, oscillator active (reset default)
'1' power down, oscillator stopped
'0' S/T awake disable (reset default)
'1' S/T awake enable. Oscillator starts on every non INFO0
must be '0'
D reset
'0' normal operation (reset default)
'1' D bits are forced to '1'
D_U enable
'0' normal operation (reset default)
'1' D channel is always send enabled regardless of E receive
force E=0 (NT mode)
'0' normal operation (reset default)
'1' E-bit send is forced to 0
'1' swap B1 and B2-channel in the S/T interface
'0' B1 send data disabled (permanent 1 sent in activated states,
Power down mode bit
must be '0'
reset default)
reset default)
This bit is not cleared by a soft reset.
Power up can only be programmed by register access
(SCTRL bit 7).
S/T signal.
bit
Cologne
Chip
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