HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 51

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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Name
CIRM
Register bit description of interrupt, status and control registers
Addr.
18h
Bits
2..0
3
4
5
6
7
r/w Function
w
w
w
w
w
w
'000'
'001'
'010'
'011'
'100'
'101'
'110'
'111'
soft reset, similar as hardware reset; the registers CIP, CIRM
and CTMT are not changed so selected I/O address is kept in
ISA-PC mode. The reset is active until the bit is cleared.
'0' deactivate reset (reset default)
'1' activate reset
select memory
'0' 32K x 8 external RAM (reset default)
'1' 8K x 8 external RAM
external interrupt enable
'0' ext. interrupt disable, IRQ_A is output (reset default)
'1' ext. interrupt enable IRQ_A is input and ored to IRQ
output
double clock mode (24.576 MHz external oscillator required)
when set, all RAM accesses are double speed
FIFO reset
The currently selected FIFO is initialised. This bit is
automatically cleared.
select IRQ channel in PC mode
IRQ disable
IRQ_A
IRQ_B
IRQ_C
IRQ_D
IRQ_E
IRQ_F
IRQ_G (only in ISA PnP mode)
Cologne
Chip
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