HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 47

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C@
4.3
Timeslots for transmit direction
Timeslots for receive direction
Data registers
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Name
B1_SSL
B2_SSL
AUX1_SSL
AUX2_SSL
Name
B1_RSL
B2_RSL
AUX1_RSL
AUX2_RSL
Name
B1_D
B2_D
AUX1_D
AUX2_D
*
Enabling more than one channel on the same slot causes undefined output data.
important!
Register bit description of GCI/IOM2 bus section
Addr.
Addr.
Addr.
2Ah
2Bh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
Bits
Bits
Bits
4..0
0..7
4..0
5
6
7
5
6
7
r/w Function
r/w Function
r/w Function
r/w read/write data registers for selected timeslot data
w
w
w
w
w
w
w
w
select GCI/IOM2 bus data lines
'0' STIO1 output
'1' STIO2 output
transmit channel enable for GCI/IOM2 bus
'0' disable (reset default)
'1' enable
select GCI/IOM2 bus data lines
'0' STIO2 is input
'1' STIO1 is input
receive channel enable for GCI/IOM2 bus
'0' disable (reset default)
'1' enable
select GCI/IOM2 bus transmission slot (0..31)
unused
select GCI/IOM2 bus receive slot (0..31)
unused
Cologne
Chip
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