HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 29

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C@
:Q^eQbi " !
*
FIFO change, FIFO reset and F1/F2 incrementation
Changing the FIFO, reseting the FIFO or incrementing the frame counters causes a short BUSY
period of the HFC-SP. This means an access to FIFO control registers is NOT allowed until BUSY
status is reset (bit 0 of STATUS register). This has a maximum duration of 25 clock cycles (2µs).
Status, interrupt and control registers can be read and written at any time.
important!
Cologne
Chip
") _V (#