HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 36

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C@
3.9.1.1 Send channels (B1, B2 and D transmit)
The send channels send data from the host bus interface to the FIFO and the HFC-SP converts the data
into HDLC code and tranfers it from the FIFO into the S/T or/and the GCI/IOM2 bus interface write
registers.
The HFC-SP checks Z1 and Z2. If Z1=Z2 (FIFO empty) the HFC-SP generates a HDLC-Flag (01111110)
and sends it to the S/T device. In this case Z2 is not incremented. If also F1=F2 only HDLC flags are sent
to the S/T interface and all counters remain unchanged. If the frame counters are unequal F2 is
incremented and the HFC-SP tries to send the next frame to the output device. After the end of a frame
(Z2 reaches Z1) it automatically generates the 16 bit CRC checksum and adds the ending flag. If there is
another frame in the FIFO (F1 F2) the F2 counter is incremented.
With every byte being sent from the host bus side to the FIFO Z1 is incremented automatically. If a
complete frame has been sent F1 must be incremented to send the next frame. If the frame counter F1 is
incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are
Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 3).
Z1(F1) is used for the frame which is just written from the PC-bus side. Z2(F2) is used for the frame
which is just beeing transmitted to the S/T device side of the HFC-SP. Z1(F2) is the end of frame pointer
of the current output frame.
In the send channels F1 is only changed from the PC interface side if the software driver wants to say
„end of send frame“. Then the current value of Z1 is stored, F1 is incremented and Z1 is used as start
address of the next frame. Z1(F2) and Z2(F2) can not be accessed.
3.9.1.2 Automatically D-channel frame repetition
The D-channel send FIFO has a special feature. If the S/T interface signals a D-channel contention
before the CRC is sent the Z2 counter is set to the starting address of the current frame and the HFC-SP
tries to repeat the frame automatically.
3.9.1.3 FIFO full condition in send channels
Due to the limited number of registers in the HFC-SP the driver software must maintain a list of frame
start and end addresses to calculate actual FIFO size and check FIFO full condition. Because there are a
maximum of 32 frame counter values and the start address of a frame is the incremented value of the end
address of the last frame the memory table must have only 32 values of 16 bits (13 bits) instead of 64.
Remember that an increment of Z-value 1FFFh is 0200h in the B-channels!
#& _V (#
*
The HFC-SP begins to transmit the bytes from a FIFO at the moment the FIFO is changed or the
F1 counter is incremented. Also changing to the FIFO that is already selected starts the
transmission. So by selecting the same FIFO again transmission can be started.
important!
:Q^eQbi " !
Cologne
Chip