HFC-U Cologne Chip AG, HFC-U Datasheet - Page 16

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

3.3
In ISA-PC mode all registers are selected by first writing the address into the Control Internal Pointer
(CIP) register. This is done by writing the HFC-U on the higher address SA0 = 1.
All consecutive read or write data accesses (SA0 = 0) are done with the selected register until the CIP
register is changed.
In processor mode all registers can be directly accessed. The registers are selected by SA0 - SA7.
3.3.1 FIFO control registers
The FIFO control registers are used to select and control the FIFOs of the HFC-U. In processor mode
the value is the address which directly selects the corresponding register.
CIP / I/O-address
10zzzzzd
10yyyyff
March 1997
yyyy
0000
0001
0010
0011
HDLC mode:
1010
1011
1100
1101
1110
1111
Transparent mode (only selectable for B-channels):
1010
1011
1100
1101
1110
1111
r) corresponding data register is read only
w) corresponding data register is write only
Register description
f: B-channel FIFO-No.:
00
01
d: D-channel FIFO-No.:
0
1
zzzzz
01000
01010
01100
01110
01001
01011
01101
01111
10001
10011
channel B1 transmit
channel B1 receive
D-channel transmit direction
D-channel receive direction
z: 5 bits for D-channel FIFO register control
y: 4 bits for B-channel FIFO register control
FIFO input counter (Z1) low byte
FIFO input counter (Z1) high byte
FIFO output counter (Z2) low byte
FIFO output counter (Z2) high byte
dummy for increment of frame counter (F1)
data write into FIFO and increment Z1
FIFO input HDLC frame counter (F1)
FIFO output HDLC frame counter (F2)
dummy for increment of frame counter (F2)
data read out of FIFO and increment Z2
data write into FIFO upside down and increment Z1
data write into FIFO and increment Z1
FIFO input HDLC frame counter (F1)
FIFO output HDLC frame counter (F2)
data read out of FIFO upside down and incremement Z2
data read out of FIFO and increment Z2
10
11
channel B2 transmit
channel B2 receive
r)
r)
r)
r)
r)
w)
r)
r)
r)
r)
w)
w)
r)
r)
r)
r)
HFC-U
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