HFC-U Cologne Chip AG, HFC-U Datasheet - Page 26

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

HFC-U
3.7
Busy synchronisation
For internal processing of the data channels and HDLC the HFC-U enters a busy phase every 125µs
on a falling F0IO edge. During this BUSY phase most of the registers must not be accessed (all FIFO
registers, B1_D, B2_D and D_D).
The minimum BUSY phase time is 280 clock cycles and the maximum BUSY phase time is 630
clock cycles.
3.7.1 Busy synchronisation with status read
Figure 5: Timing relations and delayed BUSY
The lines BUSY and DIS_BUSY are internal signals of the HFC-U. If BUSY is high the HFC-U is
in a phase when busy critical registers must not be accessed. The signal DIS_BUSY disables the start
of the internal BUSY phase until the next read/write data operation is finished. To avoid loss of data
the DIS_BUSY signal must not disable the BUSY so that the end of BUSY comes after the next
F0IO signal (see also: STATUS register bit description).
READ_STATUS symbolizes a status read operation. The high signal means the status is read. BUSY
BIT AT STATUS READ is the value returned from a read status operation (bit 0 in STATUS
register). READ/WRITE DATA ACCESS symbolizes a data read/write operation.
March 1997
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