HFC-U Cologne Chip AG, HFC-U Datasheet - Page 39

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

6.3
Timing Diagram 3: GCI/IOM timing
March 1997
SYMBOL
t
t
t
t
t
t
SRDH
SRDSU
SRDHR
SRWR
SRWRH
SRWRA
*)
*)
Clock should be symmetrical so t
GCI/IOM timing
F0IO starts one C4IO clock earlier if bit 3 in MST_MODE register is set. If this bit is set
F0IO is also awaited one C4IO clock cycle earlier.
Data Out Stable Hold Time after Clock
Data In Setup Time to Clock
Data In Hold Time after Clock
Delay Time Clock
Delay Time Clock
Data and Address Hold Time after /SRWR
CHARACTERISTICS
to /SRWR Low
to /SRWR High
LOW
= t
HIGH
MIN.
20ns
5ns
0ns
2ns
5ns
1ns
MAX.
40ns
40ns
HFC-U
–
–
–
–
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