HFC-U Cologne Chip AG, HFC-U Datasheet - Page 29

• Manufacturer Part Number: HFC-U
• Description: Isdn HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

March 1997
Name
D_D
MST_MODE (2Eh) 0
The pulseshape of the codec signals is the same as the pulseshape of the F0 signals.
The polatity of C2O can be changed by bit 1.
RESET sets register MST_MODE to '0's.
(2Ch)
Bits
6,7
1
2
3
5, 4
7, 6
r/w
w
w
w
w
w
w
w
Function
write data for D timeslot data
only bit 6 and 7 valid
GCI mode
'0'
'1'
polarity of C4O clock
'0'
'1'
polarity of F0 frame sync.
'0'
'1'
duration of F0 signal
'0'
'1'
select time slot for codec-A signal F1_A
'00'
'01'
'10'
'11'
select time slot for codec-B signal F1_B
'00'
'01'
'10'
'11'
slave (default)
C4O and F0O are inputs
master
C4O and F0O are outputs
bit cell starts with falling clock (default)
bit cell starts with rising clock
positive pulse on F0 (default)
negative pulse on F0
F0 active for one C4 clock (244ns) (default)
F0 active for two C4 clocks (488ns)
slot 0 (B1)
slot 1 (B2)
signal C2O (2.048MHz) to F1_A
disable, no pulse
slot 0 (B1)
slot 1 (B2)
slot 4 (ability to cascade HFC-U)
disable, no pule
HFC-U
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