WM8148 Wolfson Microelectronics Ltd., WM8148 Datasheet - Page 16

• Manufacturer Part Number: WM8148
• Description: WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8148
CORRELATED DOUBLE SAMPLING (CDS)
WOLFSON MICROELECTRONICS LTD
INPUT SAMPLING MODES
To suit different sensors and applications, the WM8148 can sample one, two, or three channels
simultaneously, at the rate of the VSMP clock. In each case there are two possible ratios of VSMP
frequency to the MCLK master clock frequency, and a choice of whether to use CDS. Table 1
summarises the options available, including the respective maximum sample rates. The mode of
operation is set by the Control Register bits MODE[3:0] as shown. Note MODE[0] defines whether or
not CDS is activated.
Table 1 Modes of Operation
If an external VSMP signal is not available, the WM8148 can be configured to output a
synchronisation pulse to the system by setting control bit FREE. The internally generated signal is
presented on the VSMP and/or SDO pins depending on the settings of the control bits VSMPOP and
SDO[1:0].
The input signal can be sampled in two ways: Correlated Double Sampling (CDS), or non-CDS.
CDS operation is summarised in Figure 15. The video signal processed is the difference between the
voltage applied at the RINP input when R
off, i.e. the difference between reset and video levels from the same pixel of the input signal. This
method of sampling is recommended as it removes common-mode noise.
Figure 15 CDS Reset and Video Level Sampling
In non-CDS modes, R
the reference level applied to the VRLC pin. The video signal processed is the difference between
these samples (V
the RLC DAC. In these modes d.c. variations of the input signal are not rejected.
Three-channel
(8-phase)
Three-channel
(12-phase)
Two-channel
(6-phase)
Two-channel
(8-phase)
One-channel
CDS
One-channel
non-CDS
RS
-V
RATE PER
CHANNEL
SAMPLE
(VSMP)
VS
S
MSPS
MAX
5.33
6.66
and V
). The voltage (V
10
4
4
6
S
occur simultaneously. V
FREQUENCY
MCLK/VSMP
R
RATIO
S
12
VRLC
8
6
8
6
4
S
turns off and the voltage at the RINP input when V
), on pin VRLC, may be driven externally or internally by
V
FREQENCY
MAX MCLK
S
S
MHz
samples the video signal, while R
32
48
32
48
40
40
OUTPUT
MSPS
10.66
RATE
MAX
6.66
12
12
12
10
PD Rev 4.0 April 1999
Production Data
CDS
N/A
(MODE[3:0])
12
0
8
4
2
NUMBER
MODE
S
samples
NON-
CDS
N/A
S
V
V
13
1
9
5
3
RS
VS
turns
16