WM8148 Wolfson Microelectronics Ltd., WM8148 Datasheet - Page 19

• Manufacturer Part Number: WM8148
• Description: WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8148
OVERALL SIGNAL FLOW SUMMARY
WOLFSON MICROELECTRONICS LTD
Table 2 PGAFS[1:0] Setting for Video Signal Types
If the signal exceeds the chosen range, it is clipped and the error flag OVRNG is set, which may be
output via the SDO or OP pins.
Figure 20 represents the processing of the video signal through the WM8148.
The INPUT SAMPLING BLOCK produces an effective input voltage V
difference between the input video level V
difference between the input video level V
the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V
The ADC BLOCK then converts the analogue signal, V
The digital output is then inverted if required, through the OUTPUT INVERT BLOCK to produce D
Figure 20 Overall Signal Flow
Negative-going,
VIDEO SIGNAL
Positive-going,
e.g. many CIS
V
V
V
V R L C
RLCEXT=1
IN
R E S E T
e.g. CCDs
MODE[0] = 1
Bipolar
MODE[0] = 0
TYPE
R L C
D A C
SAMPLING
RLCEXT=0
B L O C K
INPUT
+
AVDD*RLCV[3:0]/15
3
.
-
BLACK
-1.5V
0V
0V
V
SIGNAL RANGE
DIFFERENTIAL
1
OFFSET DAC
B L O C K
+ +
Offset
D A C
V
WHITE
+1.5V
A = 52/(70-PGA[5:0])
200mV*(DAC[7:0]-127.5)/127.5
2
-3V
3V
B L O C K
P G A
PGA gain
X
IN
IN
analog
V
and the voltage on the VRLC pin, V
and the input reset level V
3
PGAFS[1:0]
00, 01
+4095 codes if PGAFS[1:0]=10
+2047 codes if PGAFS[1:0]=0x
11
10
2
+0 codes if PGAFS[1:0]=11
.
3
, to a 12-bit unsigned digital output, D
V
3
x 4095/V
ADC BLOCK
OUTPUT CODE
White = 4095
White = 4095
Black = 4095
INVOP = 0
White = 0
Black = 0
Black = 0
F S
V
V
VRLC is voltage applied to VRLC pin
MODE[0], RLCEXT,RLCV[3:0], DAC[7:0],
PGA[5:0], PGAFS[1:0] and INVOP are set
by programming internal control registers.
MODE[0]=0 for CDS, 1 for non-CDS
) =
IN
R E S E T
is RINP or GINP or BINP
RESET
is V
IN
1
. For non-CDS this is the
D
digital
. For CDS, this is the
sampled during reset clamp
1
D2 = D1 if INVOP = 0
D2 =4095-D1 if INVOP = 1
VRLC
O U T P U T
INVERT
B L O C K
PD Rev 4.0 April 1999
OUTPUT CODE
, optionally set via
White = 4095
Black = 4095
Black = 4095
Production Data
INVOP = 1
White = 0
Black = 0
White = 0
D
OP[11:0]
2
1
.
2
.
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