WM8148 Wolfson Microelectronics Ltd., WM8148 Datasheet - Page 24

• Manufacturer Part Number: WM8148
• Description: WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8148
REGISTER RESET
REFERENCE VOLTAGES
DETAILED MODE TIMING DIAGRAMS
WOLFSON MICROELECTRONICS LTD
RESET ON POWER UP
To set the registers to their default values, pin NRESET must be held low during power-up. If pin
OVRD is also held low, all of the registers will be set to their default values including bits SELEN and
EN which will disable all of the analogue circuitry. If pin OVRD is held high during power up with pin
NRESET held low, all of the registers will be set to their default value with the exception of EN and
RLCEXT, which will enable all of the analogue circuitry in the device.
RESET DURING OPERATION
During device operation, pulsing NRESET low will reset all of the registers depending on the polarity
of the OVRD pin as above.
The registers may also be reset by writing to bits SRES[1:0]. This allows reset of:
The ADC reference voltages are derived from an internal bandgap reference, and buffered to
pins VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer,
and also requires decoupling. The output buffer from the RLC DAC also requires decoupling at
pin VRLC.
Peak sink and source currents of the reference buffers are typically between
depending on output voltage and current polarity. This limits the slew-rate into the decoupling
capacitors on power-up. When disabled, the buffers become high-impedance (I
decoupling capacitor voltage will not drop much during short ( 100ms) disable durations.
The following diagrams show Input Signal Sampling Diagrams, Output Data Timing and Reset
Sample/Clamp Positions for each mode of the WM8148.
INPUT SIGNAL SAMPLING DIAGRAMS
These diagrams show the required MCLK and VSMP (externally or internally generated) signals.
From these signals, internally generated signals V
levels (in CDS modes) respectively. In non-CDS modes, the reference level is sampled
simultaneously with V
from the sensor output waveform to the respective V
the arrow on the falling edge of the V
number of MCLK periods in total, and MCLK phase, which counts the number of MCLK periods
between each VSMP pulse. Note that the duration of the VSMP pulse must not include more than
one MCLK rising edge, as this will reset the phase timing. The output waveforms are included. The
position of the R
been included.
OUTPUT DATA TIMING DIAGRAMS
The output timing diagrams are used to calculate the latency through the device, which is dependent
on the operating mode. The latency can be programmed using the DEL[1:0] bits in setup register 4.
Output timing and latency does not depend on the RESREF[3:0] control bits. As an example, Figures
26 and 27 show that a sample taken on the rising edge of MCLK at time 1, will emerge from the
device on the falling edge of MCLK at time 19, i.e. a latency of 18.5 MCLK periods (DEL = 00).
RESET SAMPLE/CLAMP POSITIONS
In CDS modes, control bits RESREF[3:0] control the position of the reset sampling point, R
clamp pulse point, CL, if reset level clamping is selected. In non-CDS modes, control bits
RESREF[3:0] control the position of CL only, if reset level clamping is selected. These diagrams
show the positions to which the sampling or clamping pulse can be adjusted for each mode. Care
must be taken to adjust the R
point will be taken at the most appropriate moment during the reset portion of the input signal.
1)
2)
3)
Only the PGA Gains and Offset DAC Values registers,
All registers except power-management registers SELEN, EN, and SENBL, or
All registers, equivalent to the NRESET function.
S
pulse is programmable, therefore the RESREF[3:0] position for each diagram has
S
. The position of the sampling point is indicated by the vertical lines which run
S
position to one that will ensure that the reset sample and/or clamp
S
or R
S
pulse. Also shown is MCLK timing, which counts the
S
and R
S
or R
S
S
are used to sample the video and reset
sampling points, and by the inclusion of
PD Rev 4.0 April 1999
1mA and
Production Data
1 A), so the
S
, and the
6mA,
24