WM8148 Wolfson Microelectronics Ltd., WM8148 Datasheet - Page 35

• Manufacturer Part Number: WM8148
• Description: WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8148
WOLFSON MICROELECTRONICS LTD
Set-up Register 2
Set-up Register 3
Setup Register 4
Software Reset
b3, b2, b1, b0
RESREF[3:0]
SENBL[7:0]
BIT/WORD
CONTROL
CHAN[1:0]
SRES[1:0]
FDEL[1:0]
VSMPOP
DEL[1:0]
b7…..b0
SMALL
FREE
b7, b6
b1, b0
b1, b0
b3, b2
b4
b5
b4
b5
DEFAULT
Address
Address
Address
Address
000010
000011
000100
000101
0000
0000
0110
00
00
00
00
0
0
0
0
DESCRIPTION
Selective power enable register, activated when SELEN = 1 (Set-up Register 1).
Each bit activates respective cell when 1, de-activates when 0.
SENBL[0]
SENBL[1]
SENBL[2]
SENBL[3]
SENBL[4]
SENBL[5]
SENBL[6]
SENBL[7]
Selects the position of either the reset sample and the clamp points in CDS modes,
or the position of just the clamp pulse in non-CDS modes. See Mode Descriptions for
further details.
Enables internal clocks to be free running, without VSMP pulse input.
Reduces video and reset sample pulse widths by half an MCLK period.
Selects the input channel in One-channel (line by line) modes.
No effect when not in One-channel mode.
CHAN[1]
Writing to this register causes a software reset. There a three types of reset available:
SRES[1]
Adjusts the latency through the device in ADC clock periods.
See Detailed Mode Timing Diagrams for details.
Adjusts the latency through the device in half-MCLK increments.
FDEL[1]
In these invalid modes, output data is held constant, TVIOL is not flagged.
Enables output of internally generated MCLK/N sync pulse (only if FREE also set).
VSMPOP
Reserved for Wolfson use only, must be programmed to 0.
SMALL
FREE
0
1
0
1
0
0
1
1
0
0
1
0
0
1
1
0
1
CHAN[0]
SRES[0]
FDEL[0]
0
1
0
1
0
1
X
0
1
0
1
Requires continuous VSMP pulse input every N periods of MCLK
Free running
Bandgap/Bias
VRT, VRB buffers
VRX buffer
RLC DAC (allows VRLC to be externally driven)
Red S/H, PGA
Green S/H, PGA
Blue S/H, PGA
ADC
Default pulse widths
Reduces pulse widths
Red channel
Green channel
Blue channel
Reserved
Same action as NRESET pin
Resets all registers to default including RLCEXT.
(Except EN, SELEN and SENBL[7:0], which are
not changed)
Resets PGA and DAC only (X denotes either 1 or 0)
Default position
Earlier by MCLK/2
Later by MCLK/2
Later by MCLK/2
Requires external VSMP
VSMP pin becomes sync output
Invalid in modes 0, 1, 4 and 5
Invalid in modes 0, 1, 4 and 5
PD Rev 4.0 April 1999
Production Data
35