WM8148 Wolfson Microelectronics Ltd., WM8148 Datasheet - Page 3

• Manufacturer Part Number: WM8148
• Description: WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8148
WOLFSON MICROELECTRONICS LTD
PIN
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SCK/RNW
SEN/STB
NRESET
SDI/DNA
DGND2
AGND4
DGND4
AGND3
AGND1
AGND2
AVDD3
AVDD2
AVDD1
OVRD
NAME
VRLC
GINP
RINP
BINP
OEB
SDO
VRB
VRT
VRX
PNS
NC
NC
NC
Analogue output
Analogue output
Analogue output
Analogue input
Analogue input
Analogue input
Analogue input
Digital output
Analogue IO
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Ground
Ground
Ground
Ground
Ground
Ground
Supply
Supply
Supply
TYPE
DESCRIPTION
No internal connection.
No internal connection.
Digital ground (0V) for output drivers.
Analogue ground (0V).
Digital ground (0V).
Analogue supply (5V).
Analogue supply (5V).
Lower reference voltage. This pin must be connected to AGND and VRT via decoupling
capacitors. See Recommended External Components section for details.
Analogue ground (0V).
Upper reference voltage. This pin must be connected to AGND and VRB via decoupling
capacitors. See Recommended External Components section for details.
Input return bias voltage. This pin must be connected to AGND via decoupling
capacitors. See Recommended External Components section for details.
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
See Recommended External Components section for details. VRLC can be externally
driven if programmed Hi-Z.
Override pin. Typically tied low externally.
The sense of this pin defines the device function on reset. Refer to the description of
pin 42 for details.
Analogue ground (0V).
Red channel input video.
Green channel input video.
No internal connection.
Blue channel input video.
Analogue ground (0V).
Analogue supply (5V).
Reset input, active low. This signal forces a reset of all internal registers.
Registers are set to defaults if pin OVRD is tied low.
If pin OVRD is tied high then all registers are set to defaults except EN which is set to
1 and RLCEXT which is set to 0. This will turn on all analogue circuitry including the RLC
DAC buffers driving the VRLC pin.
Output enable control, all outputs disabled when OEB = 1.
This pin must be externally connected.
Serial Interface: register read-back,
VSMP output, setup error flag or
over-range flag (depending on control
bits SDO [1:0]).
Serial interface:
serial input data signal.
Serial interface: serial clock signal.
Serial interface: enable pulse,
active high.
Low = serial interface, High = parallel interface. This pin must be externally connected.
Parallel Interface: Hi-Z, VSMP output, set-up
error flag or over-range flag (depending on
control bits SDO [1:0]).
Parallel interface: High = data, Low = address.
Parallel interface:
High = OP[11:4] is output bus,
Low = OP[11:4] is input bus (Hi-Z).
Parallel interface: strobe, active low.
PD Rev 4.0 April 1999
Production Data
3