WM8148 Wolfson Microelectronics Ltd., WM8148 Datasheet - Page 22

• Manufacturer Part Number: WM8148
• Description: WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8148
PARALLEL INTERFACE
WOLFSON MICROELECTRONICS LTD
Figure 22 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit
address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data word
(b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK. When
the data has been shifted into the device, a pulse is applied to SEN to transfer the data
to the appropriate internal register. Note all valid registers have address bit a4 equal to 0 in
write mode.
REGISTER READ-BACK
Figure 23 Serial Interface Register Read-back
Register read-back is initiated by writing to the serial bus as described, but with address bit a4 set to
1, followed by an 8-bit dummy data word. Writing address (a5, 1, a3, a2, a1, a0) will cause the
contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register (a5, 0, a3, a2, a1, a0) to be output
MSB first on pin SDO (on the falling edge of SCK), provided control bits SDO[1:0] = 00. If SDO[1:0] is
not set to 00 then error flags will be output instead of the register contents. Note that if SDI and SDO
are not connected together, the next word may be read in to SDI while the previous word is still being
output on SDO. Alternatively, the user may tie the SDI and SDO pins together to make a 3-wire serial
interface. The user must ensure that the circuit driving SDI is Hi-Z while the SDO pin is active.
Pin OEB must be low to enable the output data word to be output.
REGISTER WRITE
Figure 24 Parallel Interface Register Write
The parallel interface uses bits [11:4] of the OP bus and the STB, DNA and RNW pins. Pin RNW
must be low during a write operation. The DNA pin defines whether the data byte is address (low) or
data (high). The 6-bit address (a5, 0, a3, a2, a1, a0) is input into OP[9:4], LSB into OP[4], (OP[10]
and OP[11] are ignored) when DNA is low, then the 8-bit data word is input into OP[11:4], LSB into
OP[4], when DNA is high. The data bus OP[11:4] for both address and data is latched in during the
low period of STB. Note all valid registers have address bit a4 equal to 0.
OP[11:4]
R N W
SDO
OEB
DNA
SCK
SEN
STB
SDI
Normal Output Data
Driven by WM8148
a 5
1
Address
a 3 a 2 a 1 a 0
Hi-Z
x
x
Address
Data Word
x
x
Driven Externally
x
x
x
x
Data
d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0
Output Data Word
Hi-Z
Normal Output Data
Driven by WM8148
PD Rev 4.0 April 1999
Production Data
22