WM8148 Wolfson Microelectronics Ltd., WM8148 Datasheet - Page 20

• Manufacturer Part Number: WM8148
• Description: WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8148
OUTPUT DATA FORMAT
WOLFSON MICROELECTRONICS LTD
CALCULATING OUTPUT FOR ANY GIVEN INPUT
The following equations describe the processing of the video and reset level signals through the
WM8148.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If MODE[0] = 0, (i.e. CDS operation) the previously sampled reset level, V
the input video.
If MODE[0] = 1, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
If RLCEXT = 1, V
If RLCEXT = 0, V
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain,
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 12-bit unsigned number, with input range configured by
PGAFS[1:0].
where the ADC full-scale range, V
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
MULTIPLEXED AND NON-MULTIPLEXED OUTPUT FORMAT
Data is output from the device, by default, as a 12-bit wide word on OP[11:0]. The output changes on
every Nth negative-going edge of MCLK where N = 2, 4, or 6 according to the video sampling mode.
This is shown as byte C in Figure 21.
If control bit MUXOP is set high, data is output in a 2 x 8-bit word format, with data changing every
Nth negative-going edge of MCLK, where N = 1, 2, or 3 according to video sampling mode. This is
shown as bytes A and B in Figure 21. Data is presented on pins OP[11:4] at twice the output pixel
rate. Bits CC[1] and CC[0] are used to indicate which channel the ADC input was taken from. Table 3
shows the channels corresponding to the CC[1:0] bit values. Bits TVIOL and OVRNG of byte B are
Error Flags, these are described below.
V
V
V
V
D
D
D
D
D
V
1
1
VRLC
2
1
1
1
2
2
3
[11:0] = INT{ (V
[11:0] = INT{ (V
[11:0] = INT{ (V
[11:0] = D
[11:0] = 4095 – D
VRLC
VRLC
=
=
=
=
=
1
1
is an externally applied voltage on pin VRLC.
is the output from the internal RLC DAC.
[11:0]
is added to the Offset DAC output.
V
V
AVDD
V
V
IN
IN
1
2
3
3
3
+ 200mV
/V
/V
/V
1
- V
- V
[11:0]
52/(70- PGA[5:0])
FS
FS
FS
RESET
VRLC
)
)
)
FS
RLCV[3:0] / 15
, = 3V.
4095} + 2047
4095}
4095} + 4095
(DAC[7:0]-127.5) / 127.5
PGAFS[1:0] = 00 or 01
PGAFS[1:0] = 11
PGAFS[1:0] = 10
(INVOP = 0)
(INVOP = 1)
RESET
, is subtracted from
PD Rev 4.0 April 1999
Eqn. 1
Eqn. 2
Eqn. 3
Eqn. 4
Eqn. 5
Eqn. 6
Eqn. 7
Eqn. 8
Eqn. 9
Eqn. 10
Production Data
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