AD1845 Analog Devices, AD1845 Datasheet - Page 21

• Manufacturer Part Number: AD1845
• Description: Parallel-port 16-Bit Soundport Stereo Codec
• Manufacturer: Analog Devices

REV. B
XCTL1:0
This register’s initial state after reset is “00xx xx00.”
ORL1:0
ORR1:0
DRS
ACI
PUR
COR
The occurrence of a PUR and/or COR is designated in the Status Register’s Sample Overrun/Underrun (SOUR) bit. The SOUR bit
is the logical OR of the COR and PUR bits. This enables a polling host CPU to detect an overrun/underrun condition while check-
ing other status bits.
This register’s initial state after reset is “0000 0000.”
Test and Initialization Register (IXA3:0 = 11)
IXA3:0
11
External Control. The state of these bits is reflected on the XCTL1:0 pins of the AD1845.
0
1
Overrange Left Detect. These bits indicate the overrange on the left capture channel. These bits change on
a sample-by-sample basis, and are read-only.
ORL1
0
0
1
1
Overrange Right Detect. These bits indicate the overrange on the right capture channel. These bits change
on a sample-by-sample basis, and are read-only.
ORR1
0
0
1
1
Data Request Status. This bit indicates the current status of the PDRQ and CDRQ pins of the AD1845.
0
1
Autocalibrate-In-Progress. This bit indicates the state of autocalibration or a recent exit from Mode Change
Enable (MCE). This bit is read-only.
0
1
Playback Underrun. For MODE1 operation, this bit is set when playback data has not arrived from the host
within one sample to be played. As a result, a midscale value will be sent to the DACs. This bit changes on a
sample by sample basis. When MODE2 is enabled, this bit is set when the playback FIFO is empty and after the
next valid sample has been played back. If this condition exists, DACZ determines the DAC playback value.
Capture Overrun. For MODE1 operation, this bit is set when the capture data has not been read by the host be-
fore the next sample arrives. The sample being read will not be overwritten by the new sample. The new sample
will be ignored. This bit changes on a sample by sample basis. In MODE2, COR is set when the capture FIFO is
full and an additional sample has been captured.
Data 7
COR
Logic LO on XCTL1:0 pins
Logic HI on XCTL1:0 pins
ORL0
0
1
0
1
ORR0
0
1
0
1
CDRQ and PDRQ are presently inactive (LO)
CDRQ or PDRQ are presently active (HI)
Autocalibration is not in progress
Autocalibration is in progress or MCE was exited within the last 128 sample periods
Data 6
Less than –1 dB underrange
Between –1 dB and 0 dB underrange
Between 0 dB and +1 dB overrange
Greater than +1 dB overrange
Less than –1 dB underrange
Between –1 dB and 0 dB underrange
Between 0 dB and +1 dB overrange
Greater than +1 dB overrange
PUR
Data 5
ACI
–21–
Data 4
DRS
Data 3
ORR1
Data 2
ORR0
Data 1
ORL1
Data 0
AD1845
ORL0