AD1845 Analog Devices, AD1845 Datasheet - Page 30

• Manufacturer Part Number: AD1845
• Description: Parallel-port 16-Bit Soundport Stereo Codec
• Manufacturer: Analog Devices

AD1845
DIRECT MEMORY ACCESS (DMA) TRANSFERS
The second type of bus cycle supported by the AD1845 are
DMA transfers. Both dual channel and single channel DMA
operations are supported. To enable Playback DMA transfers,
playback enable (PEN) must be set and PPIO cleared. To en-
able Capture DMA transfers, capture enable (CEN) must be set
and CPIO cleared. During DMA transfers, the AD1845 asserts
HI the Capture Data Request (CDRQ) or the Playback Data
Request (PDRQ) followed by the host’s asserting LO the DMA
Capture Data Acknowledge (CDAK) or Playback Data Acknowl-
edge (PDAK), respectively. The host’s asserted Acknowledge
signals cause the AD1845 to perform DMA transfers. The in-
put address lines, ADR1:0, are ignored. Data is transferred be-
tween the proper internal sample registers.
The read strobe (RD) and write strobe (WR) delimit valid data
for DMA transfers. Chip select (CS) is a “don’t care”; its state
is ignored by the AD1845.
The AD1845 may assert the Data Request signals, CDRQ and
PDRQ, at any time. Once asserted, these signals will remain ac-
tive HI until the corresponding DMA cycle occurs with the
host’s Data Acknowledge signals. The Data Request signals will
be deasserted after the falling edge of the final RD or WR strobe
in the transfer of a sample, which typically consists of multiple
bytes. See “Data Ordering” above for a definition of “sample.”
DBDIR OUTPUT
DBEN & DBDIR
DBEN OUTPUT
CDAK INPUT
PDAK INPUT
CDRQ/PDRQ
CDRQ/PDRQ
CS INPUT
RD INPUT
OUTPUTS
OUTPUTS
OUTPUTS
CS INPUT
WR INPUT
OUTPUTS
DATA7:0
DATA1:0
DATA7:0
DATA1:0
Figure 19. Control Register/PIO Write Cycle
INPUTS
Figure 18. Control Register/PIO Read Cycle
INPUTS
INPUTS
HI
t
CSSU
t
SUDK1
t
SUDK1
t
t
t
ADSU
ADSU
CSSU
t
RDDV
t
t
t
DBDL
t
STW
WDSU
t
STW
DBDL
t
t
t
CSHD
DHD2
CSHD
t
t
SUDK2
SUDK2
t
DHD1
t
t
ADHD
ADHD
–30–
DMA transfers may be independently aborted by resetting the
Capture Enable (CEN) and/or Playback Enable (PEN) bits in
the Interface Configuration Register. The current capture
sample transfer will be completed if a capture DMA is termi-
nated. The current playback sample transfer must be completed
if a playback DMA is terminated. If CDRQ and/or PDRQ are
asserted HI while the host is resetting CEN and/or PEN, the
request must be acknowledged. The host must assert CDAK
and/or PDAK LO and complete a final sample transfer.
Single-Channel DMA
Single-Channel DMA mode allows the AD1845 to be used in
systems with only a single DMA channel. It is enabled by set-
ting the SDC bit in the Interface Configuration Register. All
captures and playbacks take place on the playback channel. Ob-
viously, the AD1845 cannot perform a simultaneous capture
and playback in Single-Channel DMA mode.
Playback will occur in Single-Channel DMA mode exactly as it
does in Two-Channel mode. Capture, however, is diverted to
the playback channel which means that the capture data request
occurs on the PDRQ pin and the capture data acknowledge
must be received on the PDAK pin. The CDRQ pin will re-
main inactive LO. Any inputs to CDAK will be ignored.
Playback and capture are distinguished in Single-Channel DMA
mode by the state of the playback enable (PEN) or capture en-
able (CEN) control bits. If both PEN and CEN are set in
Single-Channel DMA mode, playback will be presumed.
To avoid confusion of the origin of a request when switching be-
tween playback and capture in Single-Channel DMA mode,
both CEN and PEN should be disabled and all pending re-
quests serviced before enabling the alternative enable bit.
Switching between playback and capture in Single-Channel
DMA mode does not require changing the PPIO and CPIO bits
or passing through the Mode Change Enable state except for
initial setup. For setup, assign zeros to both PPIO and CPIO.
This configures both playback and capture for DMA. Following
setup, switching between playback and capture can be effected
entirely by setting and clearing the PEN and CEN control bits,
a technique which avoids having to enter Mode Change Enable.
Dual-Channel DMA
The AD1845 is designed to support full duplex DMA operation
by allowing simultaneous capture and playback. The Dual-
Channel DMA feature enables playback and capture DMA re-
quests and acknowledges to occur on separate DMA channels.
Capture and playback are enabled and set for DMA transfers.
In addition, Dual-Channel DMA must be set (SDC = 0). It is
not necessary to enter MCE (Mode Change Enable) to change
PEN and CEN (Playback and Capture Enable).
DMA Timing
Below, timing parameters are shown for 8-Bit Mono Sample
Read/Capture and Write/Playback DMA transfers in Figures 20
and 21. The same timing parameters apply to multi-byte trans-
fers. The relationship between timing signals is shown in Fig-
ures 22 and 23.
The Host Interrupt Pin (INT) will go HI after a sample transfer
in which the Current Count Register underflows.
REV. B