AD1845 Analog Devices, AD1845 Datasheet - Page 29

• Manufacturer Part Number: AD1845
• Description: Parallel-port 16-Bit Soundport Stereo Codec
• Manufacturer: Analog Devices

REV. B
DATA AND CONTROL TRANSFERS
The AD1845 SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control reg-
ister accesses and for applications lacking DMA control. PIO
transfers can be made on one channel while the other is per-
forming DMA. Transfers to and from the AD1845 SoundPort
Codec are asynchronous relative to the internal data conversion
clock. Transfers are buffered by FIFOs located in the capture
and playback paths.
Data Ordering
The number of byte-wide transfers required depends on the
data format selected. The AD1845 is designed for “little
endian” formats in which the least significant byte (i.e., occupy-
ing the lowest memory address) gets transferred first. There-
fore, 16-bit data transfers require first transferring the least
significant bits [7:0] and then transferring the most significant
bits [15:8], where Bit 15 is the most significant bit in the word.
In addition, left channel data is always transferred before right
channel data with the AD1845. The following figures should
make these requirements clear.
SAMPLE 6
SAMPLE 6
SAMPLE 3
SAMPLE 3
Figure 17. 16-Bit Stereo Data Stream Sequencing
Figure 16. 16-Bit Mono Data Stream Sequencing
Figure 15. 8-Bit Stereo Data Stream Sequencing
Figure 14. 8-Bit Mono Data Stream Sequencing
BYTE 4
BYTE 4
MONO
RIGHT
BYTES 3 AND 4
BYTES 3 AND 4
SAMPLE 5
SAMPLE 3
SAMPLE 5
SAMPLE 3
MONO
RIGHT
BYTE 3
BYTE 3
MONO
SAMPLE 4
LEFT
SAMPLE 4
SAMPLE 2
SAMPLE 2
SAMPLE 2
SAMPLE 2
SAMPLE 3
SAMPLE 3
BYTE 2
BYTE 2
MONO
RIGHT
BYTES 1 AND 2
BYTES 1 AND 2
SAMPLE 1
SAMPLE 1
SAMPLE 2
SAMPLE 2
MONO
LEFT
BYTE 1
BYTE 1
MONO
LEFT
SAMPLE 1
SAMPLE 1
SAMPLE 1
SAMPLE 1
TIME
TIME
TIME
TIME
–29–
FIFO
The AD1845 includes two 16-sample deep FIFOs. The FIFOs
are built into the capture and playback paths and are completely
transparent to the user and require no programming. The
FIFOs are active in MODE1 and MODE2.
The AD1845 maintains a continuous playback stream by re-
questing data from the host until the FIFO located in the play-
back path is full. As the FIFO empties, new samples are
requested to keep the playback FIFO full. In the event that the
FIFO runs out of data and DACZ is reset to “0,” the last valid
sample will be continuously played back. If DACZ is “1,” the
AD1845 will output a midscale value.
The FIFO located in the capture data path attempts to stay
empty by making requests of the host every sample period that it
contains valid data. When the host system cannot respond dur-
ing the same sample period, the capture FIFO starts filling, and
avoids a loss of data in the audio data stream.
Data Bus Drivers
The AD1845 has built-in 8 or 16 mA bus drivers for interfacing
to the ISA bus. The drivers reduce the need for the off-chip
74_245 bus transceiver buffers in many applications. If higher
drive capability is required, 24 mA for example, the AD1845
generates the appropriate direction and enable signals. See Fig-
ure 1 and refer to the Applications Circuits section of the data
sheet.
Control and Programmed I/O (PIO) Transfers
This simpler mode of transfers is used both for control register
accesses and programmed I/O. The 37 control and PIO data
registers cannot be accessed via DMA transfers. Playback PIO
is activated when both Playback Enable (PEN) is set and Play-
back PIO (PPIO) is set. Capture PIO is activated when both
Capture Enable (CEN) is set and Capture PIO (CPIO) is set.
See Figures 18 and 19 for the detailed timing of the control
register/PIO transfers. The RD and WR signals are used to de-
fine the actual read and write cycles, respectively. The host
holds CS LO during these transfers. The DMA Capture Data
Acknowledge (CDAK) and Playback Data Acknowledge
(PDAK) must be held inactive, i.e., HI.
For read/capture cycles, the AD1845 will place data on the
DATA7:0 lines while the host is asserting the read strobe, RD,
by holding it LO. For write/playback, the host must place data
on the DATA7:0 pins while strobing the WR signal LO. The
AD1845 latches the write/playback data on the rising edge of
the WR strobe.
When using PIO data transfers, the Status Register must be
polled to determine when data should be transferred. Note that
the ADC capture data will be ready (CRDY HI) from the previ-
ous sample period shortly before the DAC playback data is
ready (PRDY HI) for the next sample period. The user should
not wait for both ADCs and DACs to become ready before initi-
ating data transfers. Instead, as soon as capture data is ready, it
should be read; as soon as the DACs are ready, playback data
should be written.
Values written to the XCTL1:0 bits in the Pin Control Register
(IXA3:0 = 10) will be reflected in the state of the XCTL1:0 ex-
ternal output pins. This feature allows a simple method for sig-
naling or software control of external logic. Changes in state of
the external XCTL pins will occur within one sample period.
Because their change is referenced to the internal sample clock,
no useful timing diagram can be constructed.
AD1845