AD1845 Analog Devices, AD1845 Datasheet - Page 28

• Manufacturer Part Number: AD1845
• Description: Parallel-port 16-Bit Soundport Stereo Codec
• Manufacturer: Analog Devices

AD1845
TOTPWD
res
XFS2:0
This register’s initial state after reset is “000x xxx0.”
CUB7:0
This register’s initial state after reset is “0000 0000.”
CLB7:0
This register’s initial state after reset is “0000 0000.”
Crystal, Clock Select/Total Power-Down Register (IXA3:0 = 29)
Capture Upper Base Count Register (IXA3:0 = 30)
Capture Lower Base Count Register (IXA3:0 = 31)
IXA3:0
IXA3:0
IXA3:0
29
30
31
Total Power Down. When TOTPWD = HI, the ADC, DAC, mixer, and voltage reference are powered down, and
Crystal/Clock Input Frequency Select. On power up or reset, the AD1845 expects a 24.576 MHz input clock. If
Capture Upper Base Count. This byte is the upper byte of the base count register containing the eight most sig-
Capture Lower Base Count. This byte is the lower byte of the base count register containing the eight least signifi-
the ADC and DAC sample clocks are turned off. Only the digital interface remains active to allow the host to exit
the AD1845 from the total power-down state.
Reserved for future expansion. Always write zeros to these bits.
the clock source connected to the AD1845 is different from the default condition, then the clock input must be se-
lected using this register. For a detailed explanation see the Power Up and Reset section of the data sheet. Figure
13 summarizes the valid input clock frequencies. Clock sources with excessive jitter may not yield optimal analog
performance.
nificant bits of the second 16-bit base register. Reads from this register return the same value which was written.
The current count contained in the counters can not be read.
cant bits of the second 16-bit base register. Reads from this register return the same value which was written. The
current count contained in the counters cannot be read.
Data 7
XFS2
Data 7
Data 7
CUB7
CLB7
CFMT
0
0
1
1
XFS2
0
0
0
0
1
1
1
1
Figure 13. Input Frequency Selection
Data 6
XFS1
Data 6
Data 6
CUB6
CLB6
CC/L
0
1
0
1
XFS1
0
0
1
1
0
0
1
1
Figure 12. Capture Audio Data Type
Data 5
XFS0
Data 5
Data 5
CUB5
CLB5
XFS0
0
1
0
1
0
1
0
1
Audio Data Type
Linear, 8-Bit Unsigned PCM
Linear, 16-Bit Twos Complement PCM
A-Law, 8-Bit Companded
-Law, 8-Bit Companded
–28–
Data 4
Data 4
Data 4
CUB4
CLB4
res
Input Frequency
24.576
14.31818 MHz
24.000
25.000
33.000
Reserved
Reserved
Reserved
Data 3
Data 3
Data 3
CUB3
CLB3
res
MHz
MHz
MHz
MHz
Data 2
Data 2
Data 2
CUB2
CLB2
res
Data 1
Data 1
Data 1
CUB1
CLB1
res
TOTPWD
Data 0
Data 0
Data 0
CUB0
CLB0
REV. B