ADSP-21060 Analog Devices, ADSP-21060 Datasheet - Page 20

• Manufacturer Part Number: ADSP-21060
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is
the bus master accessing external memory space. These switching
Parameter
Timing Requirements:
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
W = (number of wait states specified in WAIT register) × t
HI = t
H = t
NOTES
1
2
3
4
ADSP-21060/ADSP-21060L
DAD
DRLD
HDA
HDRH
DAAK
DSAK
DRHA
DARL
RW
RWR
SADADC
Data Delay/Setup: User must meet t
The falling edge of MSx, SW, BMS is referenced.
Data Hold: User must meet t
ACK Delay/Setup: User must meet t
given capacitive and dc loads.
tion of ACK (High).
CK
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
Address, Selects Delay to Data Valid
RD Low to Data Valid
Data Hold from Address, Selects
Data Hold from RD High
ACK Delay from Address, Selects
ACK Delay from RD Low
Address, Selects Hold after RD High
Address, Selects to RD Low
RD Pulsewidth
RD High to WR, RD, DMAGx Low
Address, Selects Setup before
ADRCLK High
WR, DMAG
ADDRESS
MSx, SW
ADRCLK
DATA
(OUT)
BMS
ACK
RD
HDA
2
or t
DAD
DAAK
HDRH
t
1
SADADC
or t
3
4
or t
or synchronous spec t
t
2
DRLD
DARL
DSAK
t
DAAK
or synchronous spec t
3
or synchronous specification t
2, 4
1, 2
CK.
t
DSAK
t
DAD
Min
0.5
2.0
0 + H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
0 + DT/4
HSDATI
t
. See System Hold Time Calculation under Test Conditions for the calculation of hold times
DRLD
SSDATI
ADSP-21060
.
SACKC
t
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write – Bus Master below). If
these timing requirements are met, the synchronous read/write
timing can be ignored (and vice versa).
RW
for deassertion of ACK (Low), all three specifications must be met for asser-
Max
18 + DT + W
12 + 5DT/8 + W
14 + 7DT/8 + W
8 + DT/2 + W
Min
0.5
2.0
0 + H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
0 + DT/4
ADSP-21060L
t
HDRH
t
t
HDA
DRHA
t
RWR
Max
18 + DT + W
12 + 5DT/8 + W
14 + 7DT/8 + W
8 + DT/2 + W
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns