ADSP-21060 Analog Devices, ADSP-21060 Datasheet - Page 36

• Manufacturer Part Number: ADSP-21060
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

NOTES
1
2
3
4
5
ADSP-21060/ADSP-21060L
Referenced to sample edge.
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Referenced to drive edge.
Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems.
MCE = 1, TFS enable and TFS valid follow t
DATA RECEIVE– INTERNAL CLOCK
DATA TRANSMIT– INTERNAL CLOCK
RCLK
TCLK
TFS, RFS, DT
TCLK, RCLK
RFS
TFS
DR
RCLK (INT)
DT
TCLK (INT)
TCLK (EXT)
TCLK (INT)
CLKIN
DRIVE
DRIVE
EDGE
EDGE
DT
DT
t
t
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
HOFSE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
HOFSI
HDTI
SPORT DISABLE DELAY
DRIVE EDGE
FROM INSTRUCTION
t
DFSE
t
t
DRIVE
DFSI
EDGE
DDTI
t
t
DDTEN
DDTIN
LOW TO HIGH ONLY
t
t
SCLKIW
SCLKIW
t
DCLK
t
DPTR
DDTLFSE
t
t
t
SFSI
SDRI
SFSI
and t
SAMPLE
SAMPLE
EDGE
EDGE
DDTENFS
t
t
t
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
HFSI
HDRI
HFSI
.
TFS (EXT)
TCLK / RCLK
TCLK / RCLK
DATA RECEIVE– EXTERNAL CLOCK
DATA TRANSMIT– EXTERNAL CLOCK
RCLK
TCLK
RFS
TFS
CLKIN
DR
DT
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR
MESH MULTIPROCESSING.
DRIVE
DRIVE
EDGE
EDGE
t
t
t
HOFSE
HOFSE
HDTE
DRIVE EDGE
t
t
DFSE
DFSE
DRIVE
EDGE
t
DDTE
t
t
STFSCK
DDTTI
t
DDTTE
t
t
SCLKW
SCLKW
t
t
t
t
HTFSCK
SFSE
SDRE
SFSE
SAMPLE
SAMPLE
EDGE
EDGE
t
t
t
HFSE
HDRE
HFSE