ADSP-21060 Analog Devices, ADSP-21060 Datasheet - Page 29

no-image

ADSP-21060

Manufacturer Part Number
ADSP-21060
Description
ADSP-2106x SHARC DSP Microcomputer Family
Manufacturer
Analog Devices
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21060
Manufacturer:
AD
Quantity:
2
Part Number:
ADSP-21060-CZ-160
Manufacturer:
ALLWINE
Quantity:
20 000
Part Number:
ADSP-21060BW-133X
Manufacturer:
AD
Quantity:
1
Part Number:
ADSP-21060CW-133
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-21060CW-160
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-21060CZ-133
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-21060CZ-160
Manufacturer:
AD
Quantity:
210
Part Number:
ADSP-21060CZ-160
Manufacturer:
AD31
Quantity:
116
Part Number:
ADSP-21060CZ-160
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-21060CZ-160
Manufacturer:
AD
Quantity:
40
Part Number:
ADSP-21060CZ-160
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
STSCK
HTSCK
MIENA
MIENS
MIENHG
MITRA
MITRS
MITRHG
DATEN
DATTR
ACKEN
ACKTR
ADCEN
ADCTR
MTRHBG
MENHBG
Strobes = RD, WR, SW, PAGE, DMAG.
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).
INTERFACE
MEMORY
SBTS Setup before CLKIN
SBTS Hold before CLKIN
Address/Select Enable after CLKIN
Strobes Enable after CLKIN
HBG Enable after CLKIN
Address/Select Disable after CLKIN
Strobes Disable after CLKIN
HBG Disable after CLKIN
Data Enable after CLKIN
Data Disable after CLKIN
ACK Enable after CLKIN
ACK Disable after CLKIN
ADRCLK Enable after CLKIN
ADRCLK Disable after CLKIN
Memory Interface Disable before
HBG Low
Memory Interface Enable after
HBG High
HBG
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
3
3
INTERFACE
MEMORY
ADRCLK
CLKIN
DATA
SBTS
ACK
2
2
2
2
1
t
t
1
MIENA,
ADCEN
t
MENHBG
t
MIENS,
t
ACKEN
t
DATEN
t
MIENHG
Min
12 + DT/2
–1.5 – DT/8
–1.5 – DT/8
–1.5 – DT/8
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
0 + DT/8
19 + DT
ADSP-21060
t
STSCK
and the SBTS pin. This timing is applicable to bus master tran-
sition cycles (BTC) and host transition cycles (HTC) as well as
the SBTS pin.
Max
6 + DT/2
0 – DT/4
1.5 – DT/4
2.0 – DT/4
7 – DT/8
6 – DT/8
8 – DT/4
t
HTSCK
t
t
ADCTR
MITRA,
t
t
ADSP-21060/ADSP-21060L
DATTR
ACKTR
SBTS
t
MITRS,
Min
12 + DT/2
–1.25 – DT/8
–1.5 – DT/8
–1.5 – DT/8
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
0 + DT/8
19 + DT
t
MITRHG
ADSP-21060L
Max
6 + DT/2
0 – DT/4
1.5 – DT/4
2.0 – DT/4
7 – DT/8
6 – DT/8
8 – DT/4
t
MTRHBG
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Related parts for ADSP-21060