nRF24LE1 Nordic VLSI, nRF24LE1 Datasheet - Page 121

• Manufacturer Part Number: nRF24LE1
• Manufacturer: Nordic VLSI

nRF24LE1 Preliminary Product Specification
14.4.2
During executing operation, the MDU works on its own in parallel with the MCU.
14.4.3
The Read out sequence of the first MDx registers is not critical but the last read (from MD5 - division and
MD3 - multiplication, shift or normalize) determines the end of a whole calculation (end of phase three).
14.4.4
All leading zeroes of 32-bit integer variable stored in the MD0 .. MD3 registers are removed by shift left oper-
ations. The whole operation is completed when the MSB (Most Significant Bit) of MD3 register contains a
’1’. After normalizing, bits ARCON.4 (msb) .. ARCON.0 (lsb) contain the number of shift left operations that
were done.
14.4.5
In shift operation, 32-bit integer variable stored in the MD0 ... MD3 registers (the latter contains the most sig-
nificant byte) is shifted left or right by a specified number of bits. The slr bit (ARCON.5) defines the shift
direction and bits ARCON.4... ARCON.0 specify the shift count (which must not be 0). During shift opera-
tion, zeroes come into the left end of MD3 for shifting right or they come in the right end of the MD0 for
shifting left.
14.4.6
The mdef error flag (see
the arithmetic operations is restarted or interrupted by a new operation). The error flag mechanism is auto-
matically enabled with the first write operation to MD0 and disabled with the final read instruction from MD3
(multiplication or shift/norm) or MD5 (division) in phase three.
Revision 1.1
Division 32bit/16bit
Division 16bit/16bit
Multiplication
Shift
Normalize
Operation
first read
last read
Operation
Executing calculation
Reading the result from the MDx registers
Normalizing
Shifting
The mdef flag
MD0 (lsb)
MD1
MD2
MD3 (msb)
MD4 (lsb)
MD5 (msb)
32 bit/16 bit
Table 67. on page
min. 4 clock cycles (sc <- 01h)
min. 3 clock cycles (sc = 01h)
Table 69. MDU operations execution times
Table 70. MDU registers read sequence
MD0 (lsb)
MD1 (msb)
MD4 (lsb)
MD5 (msb)
120) indicates an improperly performed operation (when one of
16 bit / 16 bit
121 of 191
Number of clock cycles
17 clock cycles
11 clock cycles
9 clock cycles
MD0 (lsb)
MD1
MD2
MD3 (msb)
16 bit x 16 bit
max 19 clock cycles (sc <- 1Fh)
max 18 clock cycles (sc = 1Fh)
MD0 (lsb)
MD1
MD2
MD3 (msb)
Shift/normalize