nRF24LE1 Nordic VLSI, nRF24LE1 Datasheet - Page 162

• Manufacturer Part Number: nRF24LE1
• Manufacturer: Nordic VLSI

nRF24LE1 Preliminary Product Specification
By default the ADC is powered down immediately after end of conversion. It can also be configured to
enter standby mode after end of conversion, and proceed to a full power-down after a programmable
delay. This shortens the wakeup time if a new conversion is initiated before the power-down delay has
elapsed. Configure the rate bits to choose behavior. Note that this automatic power-down will not clear
the pwrup bit, and the selected port pin(s) will continue to be configured as analog input(s) until the pwrup
bit is cleared from software.
A conversion can be divided into three phases: wakeup, signal acquisition and conversion. The wakeup
time depends on whether the ADC was powered down or in standby mode before initiation. If it was pow-
ered down it needs T
The sampling capacitor is switched to the analog input at the end of the wakeup phase (at t = t
remains connected throughout the acquisition phase. The sample is acquired at the end of the acquisition
phase (at t = t
The final phase is the time used by the ADC to convert the analog sample into a N-bit digital representa-
tion. This time depends on the selected resolution: T
conversions, respectively.
and resolution.
Continuous conversion mode operates exactly like single step, except that new conversions are started
automatically at a programmable rate. The converter enters power down mode between conversions to
minimize current consumption. Sampling rate is specified with the rate bits, and can be 2, 4, 8 or 16 ksps.
21.3.6
The ADC uses straight binary coding for single ended conversions. An input voltage ≤ 0V is represented by
all zeroes (000...00), and an input voltage ≥ V
followed by all zeroes (100...00).
Differential conversions use offset binary coding. A differential input voltage ≤ − V
zeroes (000...00), and an input voltage ≥ +V
followed by all zeroes (100...00).
Revision 1.1
T
0.75
ACQ
12
36
3
ADCCON1.busy
2
Output data coding
). The duration of this phase is T
6-bit
14.3
38.3
ADCCON1
3.0
5.3
ADCDATA
Starting from standby mode
WUP
8-bit
= 15µs to wake up. Otherwise, T
14.4
38.4
Table 98.
3.2
5.4
Figure 70. Timing diagram for continuous conversion
single step
write
10-bit
shows the total conversion time for all combinations of acquisition time
14.6
38.6
As for
Table 98. Single step conversion time
3.4
5.6
REF
12-bit
REF
14.8
38.8
3.6
5.8
ACQ
/2 by all ones (111...11). Zero-scale is represented by a one
162 of 191
1st value
by all ones (111...11). Midscale is represented by a one
= 0.75, 3, 12 or 36µs, selected with the tacq bits.
CONV
1/f
RATE
6-bit
17.4
19.7
28.7
52.7
= 1.7, 1.9, 2.1 and 2.3µs for 6, 8, 10 and 12-bit
WUP
Starting from power-down
= 0.6µs.
8-bit
17.6
19.9
28.9
52.9
2nd value
10-bit
1/f
17.8
20.1
29.1
53.1
RATE
REF
/2 is represented by all
12-bit
18.0
20.3
29.3
53.3
1
) and
Unit
µs
µs
µs
µs