MT57V256H36E Micron Semiconductor Products, Inc., MT57V256H36E Datasheet - Page 13

• Manufacturer Part Number: MT57V256H36E
• Description: 9Mb DDR SRAM 2.5V Vdd, HSTL Pipelined
• Manufacturer: Micron Semiconductor Products, Inc.

IEEE 1149.1 Serial Boundary Scan (JTAG)
test access port (TAP). This port operates in accor-
dance with IEEE Standard 1149.1-2001 but does not
have the set of functions required for full 1149.1 com-
pliance. These functions from the IEEE specification
are excluded because their inclusion places an added
delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not
conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 1.8V I/O logic levels.
register, boundary scan register, bypass register, and
ID register.
Disabling The JTAG Feature
JTAG feature. To disable the TAP controller, TCK must
be tied LOW (V
TDI and TMS are internally pulled up and may be
unconnected. Alternately, they may be connected to
V
unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the opera-
tion of the device.
Test Access Port (TAP)
Test Clock (TCK)
All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.
256K x 36 2.5V V
MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03
DD
The DDR SRAM incorporates a serial boundary scan
The SRAM contains a TAP controller, instruction
It is possible to operate the SRAM without using the
The test clock is used only with the TAP controller.
The TMS input is used to give commands to the TAP
through a pull-up resistor. TDO should be left
DD
, HSTL, Pipelined DDR SRAM
SS
) to prevent clocking of the device.
0.16µm Process
2.5V V
13
NOTE:
Test Data-in (TDI)
into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 7. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most signifi-
cant bit (MSB) of any register, as illustrated in Figure 8.
Test Data-out (TDO)
out from the registers. The output is active depending
upon the current state of the TAP state machine illus-
trated in Figure 7. The output changes on the falling
edge of TCK. TDO is connected to the least significant
bit (LSB) of any register, as depicted in Figure 8.
DD
The 0/1 next to each state represents the value
of TMS at the rising edge of TCK.
The TDI ball is used to serially input information
The TDO output ball is used to serially clock data-
1
0
TEST-LOGIC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RUN-TEST/
, HSTL, PIPELINED DDR SRAM
RESET
TAP Controller State Diagram
IDLE
0
1
Figure 7:
1
0
CAPTURE-DR
UPDATE-DR
PAUSE-DR
EXIT1-DR
EXIT2-DR
DR-SCAN
SHIFT-DR
1
SELECT
0
0
1
0
1
1
0
1
1
0
0
256K x 36
©2003, Micron Technology Inc.
1
0
ADVANCE
CAPTURE-IR
UPDATE-IR
PAUSE-IR
1
IR-SCAN
SHIFT-IR
EXIT1-IR
EXIT2-IR
SELECT
0
0
1
0
1
1
0
1
1
0
0