MT57V256H36E Micron Semiconductor Products, Inc., MT57V256H36E Datasheet - Page 3

• Manufacturer Part Number: MT57V256H36E
• Description: 9Mb DDR SRAM 2.5V Vdd, HSTL Pipelined
• Manufacturer: Micron Semiconductor Products, Inc.

even if that address was written in the previous cycle.
During this READ cycle, the SRAM array is bypassed,
and data is read instead from the data register storing
the recently written data. This is transparent to the
user. This feature facilitates system data coherency.
cessor, the Claymore DDR SRAM. Single data rate
operation is not supported, hence, no SD/DD# ball is
provided. Only bursts of four are supported. In addi-
tion to the echo clocks, two single-ended input clocks
are available (C and C#). The SRAM synchronizes its
output data to these data clock rising edges if pro-
vided. If not present, C and C# must be tied HIGH and
output timing is derived from K and K#. No differential
clocks are used in this device. This clocking scheme
provides greater system tuning capability than Clay-
more SRAMs and reduces the number of input clocks
required by the bus master.
Programmable Impedance Output
Buffer
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V
resistor must be five times the desired impedance. For
example, a 350 W resistor is required for an output
impedance of 70 W . To ensure that output impedance is
one-fifth the value of RQ (within 10 percent), the range
256K x 36 2.5V V
MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03
MASTER
A READ can be made immediately to an address
The DDR SRAM differs in some ways from its prede-
The DDR SRAM is equipped with programmable
ASIC)
(CPU
BUS
or
DD
, HSTL, Pipelined DDR SRAM
Return CLK#
Source CLK#
Cycle Start#
Return CLK
Source CLK
Addresses
R/W#
DQ
R = 50
SS
Vterm = 0.75V
Vterm = 0.75V
DQn
SAn
. The value of the
LD#
Application Example
SRAM
R/W#
0.16µm Process
Figure 3:
C C#
2.5V V
3
K
ZQ
K#
of RQ is 175 W to 350 W . Alternately, the ZQ ball can be
connected directly to V
device in a minimum impedance mode.
because variations may occur in supply voltage and
temperature over time. The device samples the value
of RQ. An update
the system. Impedance updates do not affect device
operation, and all data sheet timing and current speci-
fications are met during an update.
set at 50 W . To guarantee optimum output driver
impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.
Clocking
approaches. C and C# may be supplied to the SRAM to
synchronize data output across multiple devices,
enabling the bus master to receive all data simulta-
neously. If C and C# are not provided (tied HIGH) K
and K# are used as the output timing reference. The
echo clocks (CQ and CQ#) provide another alternative
for data synchronization. The echo clocks are con-
trolled exactly like the DQ signals except that CQ and
CQ# have an additional small delay for easier data cap-
ture by the bus master. Echo clocks must be separately
received for each SRAM in the system. Use of echo
clocks maximizes the available data window for each
SRAM in the system.
DD
Output impedance updates may be required
The device will power up with an output impedance
The
R = 250
Micron Technology, Inc., reserves the right to change products or specifications without notice.
, HSTL, PIPELINED DDR SRAM
DDR
SRAM
DQn
SAn
o
f the impedance is transparent to
supports
LD#
DD
Q, which will place the
SRAM
R/W#
C C#
256K x 36
flexible
©2003, Micron Technology Inc.
K
ADVANCE
ZQ
K#
clocking
R = 250