MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 12

• Manufacturer Part Number: MT29F128G08WAAC6
• Description: NAND Flash Memory
• Manufacturer: Micron

Table 1:
PDF: 09005aef8278ee3f / Source: 09005aef81f17540
16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
Symbol
ALE, ALE2
CE#, CE2#, CE3#,
CE4#
CLE, CLE2
RE#, RE2#
WE#, WE2#
WP#, WP2#
I/O[7:0], I/O[7-2:0-2]
(x8)
R/B#, R/B2#, R/B3#,
R/B4#
V
V
NC
DNU
CC
SS
Signal Descriptions
Output
Supply
Supply
Input
Input
Input
Input
Input
Input
Type
I/O
–
–
Address latch enable: During the time ALE is HIGH, address information is
transferred from I/O[7:0] into the on-chip address register on the rising edge of
WE#
Chip enable: This gates transfers between the host system and the NAND Flash
device. After the device starts a PROGRAM or ERASE operation, CE# can be de-
asserted.
For the 32Gb configuration, CE# controls the first 16Gb of memory; CE2# controls
the second 16Gb of memory. For the 64Gb configuration, CE# controls the first
32Gb of memory; CE2# controls the second 32Gb of memory. For the 128Gb
configuration, CE# controls the first 32Gb of memory; CE2# controls the second
32Gb of memory; CE3# controls the third 32Gb of memory; CE4# controls the
fourth 32Gb of memory.
See “Bus Operation,” starting on page 17, for additional operational details.
Command latch enable: When CLE is HIGH, information is transferred from
I/O[7:0] to the on-chip command register on the rising edge of WE#. When
command information is not being loaded, CLE should be driven LOW.
Read enable: This gates transfers from the NAND Flash device to the host system.
Write enable: This gates transfers from the host system to the NAND Flash device.
Write protect: Pin protects against inadvertent PROGRAM and ERASE operations.
All PROGRAM and ERASE operations are disabled when WP# is LOW.
Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction
information. Data is output only during READ operations; at other times the I/Os
are inputs.
Ready/busy: This is an open-drain, active-LOW output, that uses an external pull-
up resistor. The pin is used to indicate when the chip is processing a PROGRAM or
ERASE operation. It is also used during a READ operation to indicate when data is
being transferred from the array into the serial data register. Once these
operations have completed, R/B# returns to the high-impedance state.
In the 32Gb configuration, R/B# is for the 16Gb of memory enabled by CE#; R/B2#
is for the 16Gb of memory enabled by CE2#. In the 64Gb configuration, R/B# is for
the 32Gb of memory enabled by CE#; R/B2# is for the 32Gb of memory enabled by
CE2#.
In the 128Gb configuration, R/B# is for the 32Gb of memory enabled by CE#; R/B2#
is for the 32Gb of memory enabled by CE2#; R/B3# is for the 32Gb of memory
enabled by CE3#; R/B4# is for the 32Gb of memory enabled by CE4#.
V
V
No connect: NCs are not internally connected. They can be driven or left
unconnected.
Do not use: DNUs must be left disconnected.
CC
SS
Micron Confidential and Proprietary
: Ground connection.
: Power supply pin.
.
When address information is not being loaded, ALE should be driven LOW.
12
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16, 32, 64, 128Gb NAND Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Description
General Description
©2005 Micron Technology, Inc. All rights reserved.
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