MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 59

• Manufacturer Part Number: MT29F128G08WAAC6
• Description: NAND Flash Memory
• Manufacturer: Micron

TWO-PLANE PROGRAM PAGE 80h-11h-80h-10h
PDF: 09005aef8278ee3f / Source: 09005aef81f17540
16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
The TWO-PLANE PROGRAM PAGE (80h-11h-80h-10h) operation is similar to the PRO-
GRAM PAGE (80h-10h) operation. It programs two pages of data from the data registers
to the Flash arrays. The pages must be programmed to different planes on the same die.
Within a block, the pages must be programmed consecutively from the least significant
to most significant page address. Random page programming within a block is prohib-
ited. The first-plane address and the second-plane address must meet the two-plane
addressing requirements (see “Two-Plane Addressing” on page 55).
To begin the TWO-PLANE PROGRAM PAGE operation, write the 80h command to the
command register; write 5 ADDRESS cycles for the first plane; then write the data. Serial
data is loaded on consecutive WE# cycles starting at the given address. Next, write the
11h command. The 11h command is a “dummy” command that informs the control
logic that the first set of data for the first plane is complete. No programming of the
NAND Flash array occurs. R/B# goes LOW for
The READ STATUS (70h) command also indicates that the device is ready when status
register bit 6 is set to “1.” The only valid commands during
and 78h) and RESET (FFh).
After
for the second plane; then write the data. The PROGRAM (10h) command is written after
the second-plane data input is complete.
After the 10h command is written, the control logic automatically executes the proper
algorithm and controls all the necessary timing to program and verify the operations to
both planes. WRITE verification only detects “1s” that are not successfully written
to “0s.”
R/B# goes LOW for the duration of the array programming time (tPROG). When pro-
gramming and verification are complete, R/B# returns HIGH. The READ STATUS (70h)
command also indicates that the device is ready when status register bit 6 is set to “1.”
The only valid commands during
If a RESET (FFh) command is issued during a TWO-PLANE PROGRAM PAGE (80h-11h-
80h-10h) operation while R/B# is LOW, the data in the shared-memory cells being pro-
grammed could become invalid. Interrupting a PROGRAM operation on one page could
corrupt the data in another page within the block being programmed.
If the READ STATUS (70h) command indicates an error in the operation (status register
bit 0 is “1”), use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command
twice—once for each plane—to determine which plane operation failed.
During serial data input for either plane, the RANDOM DATA INPUT (85h) command
can be used any number of times to change the column address within that plane. For
details on this command, see “RANDOM DATA INPUT 85h” on page 38. Figure 36 on
page 60 shows TWO-PLANE PROGRAM PAGE operation.
t
DBSY, write the 80h command to the command register; write 5 ADDRESS cycles
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t
PROG are READ STATUS (70h, 78h) and RESET (FFh).
16, 32, 64, 128Gb NAND Flash Memory
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t
DBSY, then returns HIGH.
t
DBSY are READ STATUS (70h
Command Definitions
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