MT58L64L36D Micron Semiconductor, MT58L64L36D Datasheet - Page 17
MT58L64L36D
Manufacturer Part Number
MT58L64L36D
Description
(MT58LxxxLxxD) 2Mb SRAM
Manufacturer
Micron Semiconductor
Datasheet
1.MT58L64L36D.pdf
(19 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
NOT RECOMENDED FOR NEW DESIGNS
READ/WRITE TIMING PARAMETERS
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L128L18D_C.p65 – Rev. C, Pub. 11/02
BWa#-BWd#
SYM
t
f
t
t
t
t
t
t
t
KC
KF
KH
KL
KQ
KQLZ
OELZ
OEHZ
AS
ADDRESS
(NOTE 4)
(NOTE 2)
ADSC#
ADSP#
BWE#,
ADV#
OE#
CLK
CE#
D
Q
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
MIN
6.0
1.7
1.7
1.5
1.5
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
0
A1
-6
High-Z
High-Z
MAX
166
3.5
3.5
t ADSS
t CES
t AS
A2
Back-to-Back READs
t ADSH
t CEH
t KH
t AH
MIN
7.5
1.9
1.9
1.5
1.5
0
t KC
t KQLZ
(NOTE 5)
Q(A1)
-7.5
t KL
MAX
t KQ
133
4.0
4.0
Q(A2)
MIN
t OEHZ
3.2
3.2
1.5
2.2
10
0
-10
MAX
t WS
Single WRITE
t DS
D(A3)
100
5.0
4.5
READ/WRITE TIMING
A3
t DH
t WH
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
A4
17
t OELZ
PIPELINED, DCD SYNCBURST SRAM
SYM
t
t
t
t
t
t
t
t
t
ADSS
WS
DS
CES
AH
ADSH
WH
DH
CEH
2Mb: 128K x 18, 64K x 32/36
Q(A4)
MIN
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BURST READ
-6
(NOTE 1)
Q(A4+1)
MAX
Q(A4+2)
MIN
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
-7.5
MAX
Q(A4+3)
DON’T CARE
MIN
2.2
2.2
2.2
2.2
0.5
0.5
0.5
0.5
0.5
D(A5)
©2002, Micron Technology, Inc.
-10
A5
Back-to-Back
MAX
WRITEs
UNDEFINED
D(A6)
A6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns