MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 28

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

5.2
A diagram of the MT90880 device is given in Figure 10, which shows the major data and control flows between
functional components.
5.2.1
The WAN Access Interface consists of up to 32 ports, each with an input an output data stream operating at
2.048 Mbs. Alternatively, it can be configured as 8 ports operating at 8.192 Mbs. All 32 ports can operate using
a common clock (synchronous mode) or using an independent clock for each port (asynchronous mode). When
operating synchronously, the device can either operate as a slave, accepting an external clock, or as a master,
supplying the clock to the devices on the WAN Access Interface from its internal Stratum 4E DPLL. The master
clock can be locked to any of the incoming 32 frame references.
5.2.1.1
Data traffic received on the WAN Access Interface is sampled in the WAN Interface block. It is then forwarded
either to the WAN Receive block for packet assembly, or out to the TDM switch. The switch can be used both for
re-ordering timeslots before packet assembly, or to divert traffic out of the local TDM interface for processing in
a local resource pool (e.g. a DSP or other data processing unit).
The WAN Receive block can handle up to 128 active virtual channels or “contexts” simultaneously. A context
may contain any number of timeslots, from 1 to 1024. This is known as “N x 64 Kbs” trunking. Timeslots may be
added or deleted dynamically from a context to optimize network bandwidth utilization.
Basic Operation
WAN Access Interface
TDM Packet Assembly
32 ports at 2, 4, or 8 Mbit/s
Local TDM Interface
Interface &
Multiplexer
1K Switch
DPLL
WAN
Data Flows
Control Flows
Figure 10 - MT90880 Data and Control Flows
Transmit
Receive
WAN
WAN
Host Control/Data Interface
0.125 - 8 MBytes SSRAM
Control
SSRAM Interface Controller
Zarlink Semiconductor Inc.
MT90880/1/2/3
DMA
Memory Manager and
32 bit, 33 MHz PCI
(Burst or ZBT type)
Packet Memory
28
PCI Interface
Transmit
Manager
Receive
Packet
Queue
Packet
JTAG Interface
Dual Packet
JTAG Test
Controller
Interface
Admin.
MAC
Data Sheet