MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 93

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

10.5
Note 1:
Note 2:
Note 3:
Note 4:
10.6
Note 1:
Note 2:
Note 3:
System Clock Frequency
System Clock Accuracy
(synchronous mode)
System Clock Accuracy
(asynchronous mode)
TCK Frequency of Operation
TCK Cycle time
TCK Clock pulse width
TCK rise and fall time
TRST Setup time to TCK falling edge
TRST Assert time
Input data setup time
Input data hold time
TCK to Output data valid
TCK to Output data high impedance
TMS, TDI Data setup time
TMS, TDI Data hold time
TCK to TDO data valid
TCK to TDO High impedance
System Control Port
JTAG Interface
The System clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for
short durations while network synchronisation is temporarily disrupted. Drift on the system clock directly affects the Holdover
Mode accuracy. Note that the absolute system clock accuracy does not affect the Holdover accuracy, only the change in the
system clock (S_CLK) accuracy while in Holdover. For example, if the system clock oscillator has a temperature coefficient of
0.1 ppm/
of 1 ppm. The intrinsic frequency accuracy of the DPLL Holdover Mode is 0.06 ppm, excluding the system clock drift.
synchronisation signals which are based on the frequency of the master clock (S_CLK) only. The free-run frequency accuracy
of the DPLL is ± 0.005 ppm plus the accuracy of the master clock (i.e. frequency of clock output C8OB equals 8.192 MHz
± S_CLK_accuracy ± 0.005 ppm).
correctly.
The system clock frequency affects the operation of the DPLL in free-run mode. In this mode, the DPLL provides timing and
In asynchronous mode the DPLL is not used. Therefore the tolerance on S_CLK may be relaxed slightly.
TRST is an asynchronous signal. The setup time is for test purposes only
Non Test (other than TDI and TMS) signal input timing with respect to TCLK
Non Test (other than TDO) signal output timing with respect to TCLK
The absolute S_CLK accuracy must be controlled to ± 32 ppm in synchronous mode to enable the internal DPLL to function
Parameter
0
Parameter
C, a 10
0
C change in temperature while the DPLL is in the Holdover Mode will result in a frequency accuracy offset
Symbol
CLK
CLK
CLK
Table 39 - JTAG Interface
Table 38 - System Clock
ACS
ACA
t
FR
LOW
Zarlink Semiconductor Inc.
MT90880/1/2/3
Symbol
t
t
RSTSU
TPODV
t
t
t
TPSU
t
t
t
t
CYC
RST
TPH
JSU
t
JDV
TPZ
t
, t
JH
JZ
HIGH
Min.
93
Min.
40
20
10
10
15
15
Typ.
0
0
5
0
0
5
0
0
66
Typ.
Max.
± 200
10
± 32
Max.
25
30
30
15
15
Units
3
-
-
-
-
-
-
-
-
MHz
ppm
ppm
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1 and 2
Note 3
Note 4
Notes
Note 1
Note 2
Note 2
Note 3
Note 3
Notes
Data Sheet