MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 43
MT90883
Manufacturer Part Number
MT90883
Description
(MT90880 - MT90883) TDM to Packet Processors
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90883.pdf
(97 pages)
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the slave devices. The MT9088x family can also be connected as slave devices to older TDM backplanes such
as MVIP and H-MVIP buses (reference 9), either directly or through a TDM switch.
In synchronous slave mode although the DPLL is not used to sample data from the WAN TDM ports, it is still
used to provide the clocks required by the internal TDM switch. The device is able to tolerate jitter on the
primary and secondary reference clocks in excess of the G.823 and G.824 standards (references 11 and 12)
when the WAN TDM ports are run at 2.048 Mbs data rate.
H.100 / H.110
backplane
/CT_FRAME_A
/CT_FRAME_B
Figure 21 - Connecting to an H.100/H.110 Backplane in Synchronous Slave Mode
CT_STio31
CT_STio0
CT_STio1
CT_C8_A
CT_C8_B
8.192 MHz
8.192 MHz
STio0
STio1
STio31
C8_A_io
FRAME_A_io
C8_B_io
FRAME_B_io
H.100/H.110
TDM Switch
MT90866
Zarlink Semiconductor Inc.
MT90880/1/2/3
ST_CKo0
ST_CKo1
ST_FPo0
ST_FPo1
STo0
STo1
STo7
STi0
STi1
STi7
16.384 MHz
43
WAN_STI0
WAN_STO0
WAN_STI1
WAN_STO1
WAN_STI7
WAN_STO7
WAN_CLKI0
WAN_FRMI0
WAN_CLKI1
WAN_FRMI1
WAN_CLKI2
WAN_FRMI2
WAN_CLKI31
WAN_FRMI31
WAN_CLKO
WAN_FRMO
ST-bus 8.192Mbit/s mode
Slave Mode Bypass
TDM-IP Processor
DPLL
MUX
MT90880
clock and frame
internal TDM
Data Sheet
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