MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 77

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

MT90880/1/2/3
Data Sheet
Two factors affect the frequency stability while in Holdover. The first factor is the drift on the master clock
(S_CLK) frequency. Any drift in master clock frequency translates directly into drift on the holdover frequency.
Note that the absolute master clock accuracy does not affect the stability of the held frequency, only changes in
the master clock frequency while in holdover mode. For example, a 32 ppm master clock may have a
0
0
temperature coefficient of 0.1 ppm/
C. So, a 10
C change in temperature may result in an additional frequency
offset of 1 ppm, over and above the intrinsic accuracy of 0.06 ppm.
The second factor affecting stability is any large frequency jitter on the reference input prior to the reference
failure. This could cause the measured frequency to be inaccurate, resulting in an incorrect holdover frequency.
Jitter Transfer
In master mode, jitter on the incoming reference is attenuated by both a Phase Slope Limiter and the internal
Loop Filter. The Phase Slope Limiter limits the output phase slope to 7 ns per 125 µ s. Therefore, even if the
phase slope of the input signal exceeds this rate, such as for low frequency input jitter with a very large
amplitude, the maximum output phase slope will be limited to 7 ns per 125 µ s. The internal loop filter is a single
pole low-pass filter with a cutoff frequency of 1.25 Hz. This progressively attenuates all jitter above the cutoff
frequency at a rate of 20 dB/decade.
Figure 36 shows the DPLL jitter transfer function diagram across a wide range of frequencies, while Figure 37 is
the portion of the diagram from Figure 36 around 0dB of the jitter transfer amplitude. From this diagram it is
possible to see that the DPLL is a second order, type 2 PLL.
Figure 36 - DPLL Jitter Transfer Function Diagram Across a Wide Range of Frequencies
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