PM7311 pmc-sierra, PM7311 Datasheet - Page 110

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
REFCLKA
AC1FPA
DC1FPA
RXCLKA
TXCLKA
TCLKA[0,4,8]
RCLKA[0,4,8]
The SBI reference clock active bit (REFCLKA) monitors for low to high transitions on the
REFCLK input. REFCLKA is set high on a rising edge of REFCLK, and is set low when this
register is read.
The SBI Add Bus frame pulse active bit (AC1FPA) monitors for low to high transitions on
the AC1FP input. AC1FPA is set high on a rising edge of AC1FP, and is set low when this
register is read.
The SBI Drop Bus frame pulse active bit (DC1FPA) monitors for low to high transitions on
the DC1FP input. DC1FPA is set high on a rising edge of DC1FP, and is set low when this
register is read.
The Any-PHY receive clock active bit (RXCLKA) monitors for low to high transitions on the
RXCLK input. RXCLKA is set high on a rising edge of RXCLK, and is set low when this
register is read.
The Any-PHY transmit clock active bit (TXCLKA) monitors for low to high transitions on
the TXCLK input. TXCLKA is set high on a rising edge of TXCLK, and is set low when this
register is read.
The Serial Transmit Clock active bits (TCLKA) monitor for low to high transitions on the
TCLKn inputs. TCLKA is set high on a rising edge of TCLK, and is set low when this
register is read.
The Serial Receive Clock active bits (RCLKA) monitor for low to high transitions on the
RCLKn inputs. RCLKA is set high on a rising edge of RCLK, and is set low when this
register is read.
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
110