PM7311 pmc-sierra, PM7311 Datasheet - Page 49

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Pin Name
BLAST
READYB
BTERMB
WRDONEB
INTHIB
INTLOB
Type
Input
Tri-state
Output
Tri-state
Output
Output
OD
OD
Pin No.
B11
E12
D12
C12
B12
A12
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Burst Last. This signal indicates the last data access of
the transfer. When the BURSTB input is low, the BLAST
input is driven active during the last transfer of a
transaction (even if the transaction is one word in length).
When the BURSTB input is high, the BLAST input is
ignored by FREEDM 84A1024L. The BUSPOL input pin
controls the polarity of this input.
BLAST is sampled on the rising edge of BCLK.
Ready Bar. This active low signal indicates that data on
the AD[31:0] bus has been accepted (for writes), or data
on the AD[31:0] is valid (for reads). This signal may be
used by FREEDM 84A1024L to delay a data transaction.
This output is tristated one clock cycle after an FREEDM
84A1024Laccess, allowing multiple slave devices to be
tied together in the system. This output should be pulled
up externally.
READYB is updated on the rising edge of BCLK.
Burst Terminate Bar. This signal is asserted low by
FREEDM 84A1024L when a data transfer has reached
the address boundary of a burstable range. The
maximum burst range supported is 4. Attempts to extend
the burst transfer after this signal is asserted will be
ignored. This output is tristated one clock cycle after an
FREEDM 84A1024Laccess, allowing multiple slave
devices to be tied together in the system. This output
should be pulled up externally.
BTERMB is updated on the rising edge of BCLK.
Write Done Bar. This signal is asserted low by FREEDM
84A1024Lwhen the most recent write access to internal
registers is complete. This signal may be used by
external circuitry to delay the issuance of a write
operation address cycle until FREEDM 84A1024Lcan
accept write data. This signal is only needed in systems
where the READYB output cannot be used to delay a
write data transaction (due to microprocessor
restrictions).
WRDONEB is updated on the rising edge of BCLK.
goes low when a FREEDM 84A1024L high priority
interrupt source is active and that source is unmasked.
The FREEDM 84A1024Lmay be enabled to report many
alarms or events via interrupts. INTHIB becomes high
impedance when the interrupt is acknowledged via an
appropriate register access.
INTHIB is an asynchronous signal.
Active Low Open-Drain Low Priority Interrupt. This signal
goes low when a FREEDM 84A1024L low priority
interrupt source is active and that source is unmasked.
The FREEDM 84A1024Lmay be enabled to report many
alarms or events via interrupts. INTLOB becomes high
impedance when the interrupt is acknowledged via an
appropriate register access.
INTLOB is an asynchronous signal.
Function
Active Low Open-Drain High Priority Interrupt. This signal
Released
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