ST7571 Sitronix Technology, ST7571 Datasheet - Page 17

• Manufacturer Part Number: ST7571
• Description: 4 Gray Scale Dot Matrix LCD Controller/Driver
• Manufacturer: Sitronix Technology

www.DataSheet4U.com
ST7571
4-Line SPI Mode (PS0 = “L”, PS1 = “H”, PS2 = “L”)
When IC is active (CSB=“L”), serial data (SID) and serial clock (SCLK) inputs are enabled. When ST7571 is not active
(CSB=“H”), the internal 8-bit shift register and 3-bit counter are reset. The display data/command indication is controlled by
the register selection pin (A0). The signals transferred on data bus will be display data when A0 is high and will be
instruction when A0 is low. The read feature is not supported. Serial data on SID is latched at the rising edge of serial clock
on SCLK. After the 8
pointer will be increased by one automatically after each byte of DDRAM access.
3-Line SPI Mode (PS0 = “L”, PS1 = “L”, PS2= “L”)
In 3-Line mode, default message from MCU is command. The Display Data Length command (2 bytes command) must be
set before writing display data into Display Data RAM, after the display data is sent over, the next message is turned to be
command. Signals on SID are latched at the rising edge of SCLK. After receiving 8-bit display data, the column address
pointer of DDRAM will be increased by one automatically.
“Set Display Data Length” is used in 3-Line SPI mode only. It is 2-byte instruction: the first one informs the LCD driver and
the second one sets the counter of input data (in bytes). After these two commands, the following messages will be data, till
the data counter is cleared. If data is stopped during transmitting, it is not a valid data. A new data (8 bits) must write again.
NOTE: If CSB is “H” before the end of a transmission, it stops this transfer and the next access should be re-initialized.
Ver 1.5a
(1) Set Page and Column Address.
(2) Set Display Data Length (DDL) command and No. of Data Bytes.
(3) This figure is an example for 104 Data bytes to be transferred.
Set Page Address
Set Column Address MSB
Set Column Address LSB
Set Display Data Length (DDL)
Set No. of Data Bytes
th
serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address
Command
Command
Fig. 4 3-Line SPI Timing (A0 is not used)
Fig. 3 4-line SPI Timing
DB7
DB7
1
0
0
1
17/76
DB6
DB6
0
0
0
1
Display Data Length (bytes)
DB5
DB5
1
0
0
1
DB4
DB4
1
1
0
0
DB3
DB3
P3
X4
0
1
DB2
DB2
P2
X7
X3
0
DB1
DB1
P1
X6
X2
0
DB0
DB0
P0
X5
X1
0
2009/7/21