ST7571 Sitronix Technology, ST7571 Datasheet - Page 18
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ST7571
Manufacturer Part Number
ST7571
Description
4 Gray Scale Dot Matrix LCD Controller/Driver
Manufacturer
Sitronix Technology
Datasheet
1.ST7571.pdf
(76 pages)
- Current page: 18 of 76
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ST7571
I
The I
Data line (SDA) and a Serial Clock line (SCLK). Both lines must be connected with a pull-up resistor which drives SDA and
SCLK to high when the bus is not busy. Data transfer can be initiated only when the bus is not busy.
The I
the commands sent via the I
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of
the clock pulse because changes of SDA line at this time will be interpreted as START or STOP. Bit transfer is illustrated in
Fig 5.
START AND STOP CONDITIONS
Both SDA and SCLK lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of SDA, while SCLK is HIGH
is defined as the START condition (S). A LOW-to-HIGH transition of SDA while SCLK is HIGH is defined as the STOP
condition (P). The START and STOP conditions are illustrated in Fig 6.
Ver 1.5a
2
C Interface (PS0= “L”, PS1= “L”, PS2= “H”)
2
2
C Interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial
C interface of ST7571 supports write access and read of acknowledge-bit. The I
2
C Interface. It also receives RAM data and sends it to the Display RAM.
Fig 6. Definition of START and STOP conditions
Fig 5. Bit transfer
18/76
2
C interface receives and executes
2009/7/21
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