ST7571 Sitronix Technology, ST7571 Datasheet - Page 19

• Manufacturer Part Number: ST7571
• Description: 4 Gray Scale Dot Matrix LCD Controller/Driver
• Manufacturer: Sitronix Technology

ST7571
SYSTEM CONFIGURATION
The system configuration is illustrated in Fig 7 and some word-definitions are explained below:
- Transmitter: the device which sends the data to the bus.
- Receiver: the device which receives the data from the bus.
- Master: the device which initiates a transfer, generates clock signals and terminates a transfer.
- Slave: the device which is addressed by a master.
- Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message.
- Arbitration: the procedure to ensure that, if more than one master tries to control the bus simultaneously, only one is
allowed to do so and the message is not corrupted.
- Synchronization: procedure to synchronize the clock signals of two or more devices.
Fig 7. System configuration
ACKNOWLEDGEMENT
Each byte of eight bits is followed by an acknowledge-bit. The acknowledge-bit is a HIGH signal put on SDA by the
transmitter during the time when the master generates an extra acknowledge-related clock pulse. A slave receiver which is
addressed must generate an acknowledge-bit after the reception of each byte. A master receiver must also generate an
acknowledge-bit after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges must pull-down the SDA line during the acknowledge-clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal an end-of-data to the slave transmitter by not generating a acknowledge-bit on the last byte that has
been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a
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STOP condition. Acknowledgement on the I
C Interface is illustrated in Fig 8.
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Fig 8. Acknowledgement of I
C Interface
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I
C INTERFACE PROTOCOL
ST7571 supports command/data write to addressed slaves on the bus.
www.DataSheet4U.com
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Before any data is transmitted on the I
C Interface, the device, which should respond, is addressed first. Four 7-bit slave
addresses (0111100, 0111101, 0111110 and 0111111) are reserved for ST7571. The least significant 2 bits of the slave
address is set by connecting SA0 and SA1 to either logic 0 (VSS1) or logic 1 (VDD1).
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The I
C Interface protocol is illustrated in Fig 9.
Ver 1.5a
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2009/7/21