ST7571 Sitronix Technology, ST7571 Datasheet - Page 22

• Manufacturer Part Number: ST7571
• Description: 4 Gray Scale Dot Matrix LCD Controller/Driver
• Manufacturer: Sitronix Technology

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Column Address
Internal column
Display Data
Display data
ST7571
7.2 DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 129-row by 128-column addressable array. Each pixel can be
selected when the page and column addresses are specified. The 129 rows are divided into 16 pages of 8 lines and the 17
page with a single line (DB0 only). Data is written to the 8 lines of each page directly through DB0 to DB7. The display data
of DB0 to DB7 from the microprocessor correspond to the LCD common lines. The LCD controller and MPU interface
operate independently, data can be written into RAM at the same time when data is being displayed without flicker on LCD.
Page Address Circuit
It incorporates 4-bit Page Address register changed by only the “Set Page” instruction. Page Address 16 is a special RAM
area for the icons and display data DB0 is only valid. The page address is set from 0 to 15, and Page 16 is for Icon page.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line
Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of
on-chip RAM. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter
circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL
signal and generates the line address for transferring the 128-bit RAM data to the display data latch circuit. When icon is
enabled by setting icon control register, display data of icons are not scrolled because the MPU can not access Line
Address of icons.
Column Address Circuit
When set Column Address MSB / LSB instruction is issued, 7-bit (X[7:1]) are set and lowest bit (X0) is set to “0”. The
internal column address (X[7:0]) is increased by 1 automatically after each byte of data access (write data). After sequential
access twice, the column address (X[7:1]) will point to the next column address. Please refer to Fig. 12.
Segment Control Circuit
This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF
instructions without changing the data in the Display Data RAM.
SEG Output
Ver 1.5a
LCD panel
LCD panel
address
(MX=0)
(MX=1)
display
display
X[7:1]
X[7:0]
Fig. 12 The Relationship between the Column Address and The Segment Outputs
00
1
0
SEG
00H
0
01
1
0
02
1
0
SEG
01H
1
03
0
1
04
0
1
SEG
02H
2
05
1
0
06
0
1
22/76
SEG
03H
3
07
0
1
…
…
…
…
…
…
…
F8
1
0
SEG
7CH
124
F9
1
0
FA
1
0
SEG
7DH
125
FB
0
1
FC
0
1
SEG
7EH
126
FD
1
0
2009/7/21
FE
0
1
SEG
7FH
127
FF
th
0
1