IDT82V2044E Integrated Device Technology, IDT82V2044E Datasheet - Page 20

• Manufacturer Part Number: IDT82V2044E
• Description: 4 Channel T1/j1/e1 Short Haul Liu
• Manufacturer: Integrated Device Technology

QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
3.3.2
ing on channels located in other chips can be performed by tapping the mon-
itored channel through a high impedance bridging circuit. Refer to
9
RRINGn is dramatically attenuated. To compensate this attenuation, the
Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB,
selected by MG[1:0] bits (RCF2, 09H...). For normal operation, the Monitor
Gain should be set to 0 dB.
3.3.3
tivity and to allow programming of the LOS level up to -24 dB. See section
3.5 LOS AND AIS DETECTION. It can be enabled or disabled by setting
EQ_ON bit to ‘1’ or ‘0’ (RCF1, 08H...).
and Figure-10.
Figure-9 Monitoring Receive Line in Another Chip
In both T1/J1 and E1 short haul applications, the non-intrusive monitor-
After a high resistance bridging circuit, the signal arriving at the RTIPn/
The Adaptive Equalizer can be enabled to increase the receive sensi-
Figure-10 Monitor Transmit Line in Another Chip
LINE MONITOR
ADAPTIVE EQUALIZER
DSX cross connect
DSX cross connect
point
point
R
R
TTIP
RTIP
RRING
TRING
RRING
RRING
RTIP
RTIP
=22/26/32dB
monitor gain
monitor gain
normal transmit mode
normal receive mode
monitor mode
gain=0dB
=22/26/32dB
monitor
monitor gain
monitor mode
Figure-
20
3.3.4
tive Equalizer enabled, the receive sensitivity will be -20 dB.
3.3.5
space according to the amplitude of the input signals. The threshold can
be 40%, 50%, 60% or 70%, as selected by the SLICE[1:0] bits (RCF2,
09H...). The output of the Data Slicer is forwarded to the CDR (Clock & Data
Recovery) unit or to the RDPn/RDNn pins directly if the CDR is disabled.
3.3.6
recovered clock tracks the jitter in the data output from the Data Slicer and
keeps the phase relationship between data and clock during the absence
of the incoming pulse. The CDR can also be by-passed in the Dual Rail
mode. When CDR is by-passed, the data from the Data Slicer is output to
the RDPn/RDNn pins directly.
3.3.7
select the AMI decoder or B8ZS decoder. In E1 applications, the R_MD[1:0]
bits (RCF0, 07H...) are used to select the AMI decoder or HDB3 decoder.
3.3.8
pin and RDNn pin. In E1 mode, the RCLKn outputs a recovered 2.048 MHz
clock. In T1/J1 mode, the RCLKn outputs a recovered 1.544 MHz clock. The
received data is updated on the RDn/RDPn and RDNn pins on the active
edge of RCLKn. The active edge of RCLKn can be selected by the
RCLK_SEL bit (RCF0, 07H...). And the active level of the data on RDn/
RDPn and RDNn can also be selected by the RD_INV bit (RCF0, 07H...).
Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 07H...). In Sin-
gle Rail mode, only RDn pin is used to output data and the RDNn/CVn pin
is used to report the received errors. In Dual Rail Mode, both RDPn pin and
RDNn pin are used for outputting data.
R_MD[1:0] to ‘11’ (binary). In this situation, the output data from the Data
Slicer will be output to the RDPn/RDNn pins directly, and the RCLKn out-
puts the exclusive OR (XOR) of the RDPn and RDNn.
3.3.9
bit (RCF0, 07H...) to ‘1’. In this case, the RCLKn, RDn/RDPn, RDPn and
LOSn will be logic low.
The Receive Sensitivity for both E1 and T1/J1 is -10 dB. With the Adap-
The Data Slicer is used to generate a standard amplitude mark or a
The CDR is used to recover the clock from the received signals. The
In T1/J1 applications, the R_MD[1:0] bits (RCF0, 07H...) is used to
The receive path system interface consists of RCLKn pin, RDn/RDPn
The received data can be output to the system side in two different ways:
In the receive Dual Rail mode, the CDR unit can be by-passed by setting
The receive path can be powered down individually by setting R_OFF
RECEIVE SENSITIVITY
DATA SLICER
CDR (Clock & Data Recovery)
DECODER
RECEIVE PATH SYSTEM INTERFACE
RECEIVE PATH POWER DOWN
TEMPERATURE RANGES
INDUSTRIAL