IDT82V2044E Integrated Device Technology, IDT82V2044E Datasheet - Page 4

• Manufacturer Part Number: IDT82V2044E
• Description: 4 Channel T1/j1/e1 Short Haul Liu
• Manufacturer: Integrated Device Technology

QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
4
5
6
7
3.9
3.10
3.11
3.12
3.13
3.14
3.15
PROGRAMMING INFORMATION .............................................................................................. 33
4.1
4.2
IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 52
5.1
5.2
TEST SPECIFICATIONS ............................................................................................................ 56
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 68
7.1
7.2
3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 28
3.8.2 ERROR DETECTION AND COUNTING ................................................................ 28
3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 29
LINE DRIVER FAILURE MONITORING ........................................................................... 29
MCLK AND TCLK ............................................................................................................. 30
3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 30
3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 30
MICROCONTROLLER INTERFACES ............................................................................. 31
3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 31
3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 31
INTERRUPT HANDLING .................................................................................................. 32
5V TOLERANT I/O PINS .................................................................................................. 32
RESET OPERATION ........................................................................................................ 32
POWER SUPPLY ............................................................................................................. 32
REGISTER LIST AND MAP ............................................................................................. 33
REGISTER DESCRIPTION .............................................................................................. 35
4.2.1 GLOBAL REGISTERS............................................................................................ 35
4.2.2 JITTER ATTENUATION CONTROL REGISTER ................................................... 37
4.2.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 38
4.2.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 40
4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 42
4.2.6 INTERRUPT CONTROL REGISTERS ................................................................... 45
4.2.7 LINE STATUS REGISTERS ................................................................................... 47
4.2.8 INTERRUPT STATUS REGISTERS ...................................................................... 49
4.2.9 COUNTER REGISTERS ........................................................................................ 50
4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 51
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 53
JTAG DATA REGISTER ................................................................................................... 53
5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 53
5.2.2 BYPASS REGISTER (BR)...................................................................................... 53
5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 53
5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 54
SERIAL INTERFACE TIMING .......................................................................................... 68
PARALLEL INTERFACE TIMING ..................................................................................... 69
4
TEMPERATURE RANGES
INDUSTRIAL