IDT82V2044E Integrated Device Technology, IDT82V2044E Datasheet - Page 40

• Manufacturer Part Number: IDT82V2044E
• Description: 4 Channel T1/j1/e1 Short Haul Liu
• Manufacturer: Integrated Device Technology

QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
4.2.4
Table-32 RCF0: Receiver Configuration Register 0
Table-33 RCF1: Receiver Configuration Register 1
RCLK_SEL
R_MD[1:0]
LOS[4:0]
Symbol
RD_INV
Symbol
EQ_ON
R_OFF
RECEIVE PATH CONTROL REGISTERS
-
-
-
(R/W, Address = 08H,48H,88H,C8H)
(R/W, Address = 07H,47H,87H,C7H)
7-5
1-0
4-0
Bit
Bit
4
3
2
7
6
5
Default
Default
10101
000
00
0
0
0
0
0
0
Receiver power down enable
Receive data invert
Receive clock edge select (this bit is ignored in slicer mode)
Receiver path decoding selection
Reserved
= 0: Receiver power up
= 1: Receiver power down
= 0: data on RDn or RDPn/RDNn is active high
= 1: data on RDn or RDPn/RDNn is active low
= 0: data on RDn or RDPn/RDNn is updated on the rising edges of RCLKn
= 1: data on RDn or RDPn/RDNn is updated on the falling edges of RCLKn
= 00: receive data is HDB3 (E1) / B8ZS (T1/J1) decoded and output on RDn with single rail NRZ format
= 01: receive data is AMI decoded and output on RDn with single rail NRZ format
= 10: decoder is bypassed, re-timed dual rail data with NRZ format output on RDPn/RDNn (dual rail mode with
clock recovery)
= 11: both CDR and decoder blocks are bypassed, slicer data with RZ format output on RDPn/RDNn (slicer mode)
Reserved
= 0: receive equalizer off
= 1: receive equalizer on (LOS programming enabled)
Reserved. Should be 0 for normal operation.
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011 - 11111
40
LOS Clear Level (dB)
0
>-2
>-4
>-6
>-8
>-10
>-12
>-14
>-16
>-18
>-20
Reserved
Description
Description
LOS Declare Level (dB)
<-4
<-6
<-8
<-10
<-12
<-14
<-16
<-18
<-20
<-22
<-24
TEMPERATURE RANGES
INDUSTRIAL